From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.28567.1585185792966676427 for ; Wed, 25 Mar 2020 18:23:13 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: jiewen.yao@intel.com) IronPort-SDR: 1alVURamh87RyMyug/G5+7iipOP6yIjrmb6n/5nek6H5brXD9GdAdeKKcMJK6NH4+1r+PbFtku Q07HSBTkv/kg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2020 18:23:12 -0700 IronPort-SDR: RK9wbGuKFKuvHqR4aFhCYL2mh12Lq0oUO8tXuFsO93SeE2IEGMwCFK07IKde0yalI6x5f2Xo7r lsLRyWDKtn+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,306,1580803200"; d="scan'208";a="240802079" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga008.jf.intel.com with ESMTP; 25 Mar 2020 18:23:12 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 25 Mar 2020 18:23:12 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 25 Mar 2020 18:23:11 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.50]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.43]) with mapi id 14.03.0439.000; Thu, 26 Mar 2020 09:23:08 +0800 From: "Yao, Jiewen" To: "devel@edk2.groups.io" , "Yao, Jiewen" , "Zurcher, Christopher J" CC: "Wang, Jian J" , "Lu, XiaoyuX" , Eugene Cohen , Ard Biesheuvel Subject: Re: [edk2-devel] [PATCH 1/1] CryptoPkg/OpensslLib: Add native instruction support for IA32 and X64 Thread-Topic: [edk2-devel] [PATCH 1/1] CryptoPkg/OpensslLib: Add native instruction support for IA32 and X64 Thread-Index: AQHV/Ebi1gaDbPZSX0eeh8s0KfCdQqhaHaDggAAChCA= Date: Thu, 26 Mar 2020 01:23:07 +0000 Message-ID: <74D8A39837DF1E4DA445A8C0B3885C503F99C64F@shsmsx102.ccr.corp.intel.com> References: <20200317102656.20032-1-christopher.j.zurcher@intel.com> <20200317102656.20032-2-christopher.j.zurcher@intel.com> <15FFB5A5A94CCE31.23217@groups.io> In-Reply-To: <15FFB5A5A94CCE31.23217@groups.io> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: jiewen.yao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Some more comment: 3) Do you consider to enable RNG instruction as well? 4) I saw you added some code for AVX instruction, such as YMM register. Have you validated that code, to make sure it can work correctly in curren= t environment? > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Yao, Jiew= en > Sent: Thursday, March 26, 2020 9:15 AM > To: devel@edk2.groups.io; Zurcher, Christopher J > > Cc: Wang, Jian J ; Lu, XiaoyuX ; > Eugene Cohen ; Ard Biesheuvel > Subject: Re: [edk2-devel] [PATCH 1/1] CryptoPkg/OpensslLib: Add native > instruction support for IA32 and X64 >=20 > HI Christopher > Thanks for the contribution. I think it is good enhancement. >=20 > Do you have any data show what performance improvement we can get? > Did the system boot faster with the this? Which feature ? > UEFI Secure Boot? TCG Measured Boot? HTTPS boot? >=20 >=20 > Comment for the code: > 1) I am not sure if we need separate OpensslLibIa32 and OpensslLibX64. > Can we just define single INF, such as OpensslLibHw.inf ? >=20 > 2) Do we also need add a new version for OpensslLibCrypto.inf ? >=20 >=20 >=20 > Thank you > Yao Jiewen >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Zurcher= , > > Christopher J > > Sent: Tuesday, March 17, 2020 6:27 PM > > To: devel@edk2.groups.io > > Cc: Wang, Jian J ; Lu, XiaoyuX > ; > > Eugene Cohen ; Ard Biesheuvel > > Subject: [edk2-devel] [PATCH 1/1] CryptoPkg/OpensslLib: Add native > instruction > > support for IA32 and X64 > > >=20 >=20 >=20