From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.523.1654645545371118433 for ; Tue, 07 Jun 2022 16:45:46 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=RnhIxelF; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: isaac.w.oram@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654645545; x=1686181545; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ARG+PIS4ua95ZNQBjsxnUcKacDsiRU/cd4GL5exKaKA=; b=RnhIxelFnhRQ8NzvJy5Xuo86iKQ9wG6pR30zakPCZLUQUgegiLwleVpk F5ZUkNeIfkld+ZU5bl2w8JYRBdL0zaizWARrDaJoo+NHRmmamJBefFa2I yzUTVLT1KmHoFYORec4qGed7HoJ7qluWbnh6r1cWYG53tOujdCGlY8AtM YJ6kZD8tgp0qh2cNFGCPngcYHAt2o5P17ziJAgCL048DA7r028cX0KeHA RR2V9//lGMdyXYqxvlbGg3G/eIPePvas+lQvgawMTnYCFt793buXyamOz f9VYh2BRJIxipN2fn+ZBQ6UVLoNJClDU5db1TsTD9OtFZAuEdliqT3UKc Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10371"; a="340761336" X-IronPort-AV: E=Sophos;i="5.91,284,1647327600"; d="scan'208";a="340761336" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2022 16:45:40 -0700 X-IronPort-AV: E=Sophos;i="5.91,284,1647327600"; d="scan'208";a="826612839" Received: from iworam-desk.amr.corp.intel.com ([10.24.80.243]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2022 16:45:39 -0700 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V2 1/1] WhitleySiliconPkg/PchPolicyPpi: Fix binary structure layout Date: Tue, 7 Jun 2022 16:45:29 -0700 Message-Id: <75465408b8a1cf0d269a2b1d2ea7707b6731893e.1654645346.git.isaac.w.oram@intel.com> X-Mailer: git-send-email 2.36.1.windows.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit V2: Use UINT8 instead of BOOLEAN for DmiStopAndScreamEnable and Rsvdbits2 V1: Disambiguate the PCH_DMI_CONFIG and PCH_TRACE_HUB_CONFIG structure definitions such that compilers generate same binary layouts. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram --- .../Pch/SouthClusterLbg/Include/PchPolicyCommon.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h index 0e10d0b8f0..11057a3ace 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h @@ -1351,7 +1351,9 @@ typedef struct { **/ UINT32 DmiAspm : 1; UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable DMI Power Optimizer on PCH side. - BOOLEAN DmiStopAndScreamEnable : 1; + UINT32 Rsvdbits1 : 30; + UINT8 DmiStopAndScreamEnable : 1; + UINT8 Rsvdbits2 : 7; UINT32 DmiLinkDownHangBypass : 1; UINT32 Rsvdbits : 29; UINT32 Rsvd0[6]; ///< Reserved bytes @@ -1447,6 +1449,7 @@ typedef struct { TRACE_HUB_CONFIG TraceHub; UINT32 AetEnableMode : 2; UINT32 PchTraceHubHide : 1; + UINT32 Rsvdbits : 29; } PCH_TRACE_HUB_CONFIG; -- 2.36.1.windows.1