From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5541D2041D9E0 for ; Wed, 29 Mar 2017 06:37:15 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 5DB397E9CD; Wed, 29 Mar 2017 13:37:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 5DB397E9CD Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 5DB397E9CD Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-134.phx2.redhat.com [10.3.116.134]) by smtp.corp.redhat.com (Postfix) with ESMTP id A88629665E; Wed, 29 Mar 2017 13:37:00 +0000 (UTC) To: "Michael S. Tsirkin" References: <58D17AF0.2010802@arm.com> <20170321193933.GB31111@cbox> <58DA3F68.6090901@arm.com> <20170328112328.GA31156@cbox> <20170328115413.GJ23682@e104320-lin> <58DA67BA.8070404@arm.com> <5b7352f4-4965-3ed5-3879-db871797be47@huawei.com> <20170329103658.GQ23682@e104320-lin> <2a427164-9b37-6711-3a56-906634ba7f12@redhat.com> <20170329154539-mutt-send-email-mst@kernel.org> Cc: Achin Gupta , gengdongjiu , ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, qemu-devel@nongnu.org, zhaoshenglong@huawei.com, James Morse , Christoffer Dall , xiexiuqi@huawei.com, Marc Zyngier , catalin.marinas@arm.com, will.deacon@arm.com, christoffer.dall@linaro.org, rkrcmar@redhat.com, suzuki.poulose@arm.com, andre.przywara@arm.com, mark.rutland@arm.com, vladimir.murzin@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, wangxiongfeng2@huawei.com, wuquanming@huawei.com, huangshaoyu@huawei.com, Leif.Lindholm@linaro.com, nd@arm.com, Igor Mammedov From: Laszlo Ersek Message-ID: <756e3032-e619-a70d-3e29-d2797e52fecf@redhat.com> Date: Wed, 29 Mar 2017 15:36:59 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20170329154539-mutt-send-email-mst@kernel.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Wed, 29 Mar 2017 13:37:14 +0000 (UTC) Subject: Re: [PATCH] kvm: pass the virtual SEI syndrome to guest OS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Mar 2017 13:37:15 -0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit On 03/29/17 14:51, Michael S. Tsirkin wrote: > On Wed, Mar 29, 2017 at 01:58:29PM +0200, Laszlo Ersek wrote: >> (8) When QEMU gets SIGBUS from the kernel -- I hope that's going to come >> through a signalfd -- QEMU can format the CPER right into guest memory, >> and then inject whatever interrupt (or assert whatever GPIO line) is >> necessary for notifying the guest. > > I think I see a race condition potential - what if guest accesses > CPER in guest memory while it's being written? I'm not entirely sure about the data flow here (these parts of the ACPI spec are particularly hard to read...), but I thought the OS wouldn't look until it got a notification. Or, are you concerned about the next CPER write by QEMU, while the OS is reading the last one (and maybe the CPER area could wrap around?) > > We can probably use another level of indirection to fix this: > > allocate twice the space, add a pointer to where the valid > table is located and update that after writing CPER completely. > The pointer can be written atomically but also needs to > be read atomically, so I suspect it should be a single byte > as we don't know how are OSPMs implementing this. > A-B-A problem? (Is that usually solved with a cookie or a wider generation counter? But that would again require wider atomics.) I do wonder though how this is handled on physical hardware. Assuming the hardware error traps to the firmware first (which, on phys hw, is responsible for depositing the CPER), in that scenario the phys firmware would face the same issue (i.e., asynchronously interrupting the OS, which could be reading the previously stored CPER). Thanks, Laszlo