[Patch][edk2-platforms/devel-MinnowBoard3] Fixed some GCC build errors.

* [Patch][edk2-platforms/devel-MinnowBoard3] Fixed some GCC build errors.
@ 2017-05-11  2:24 zwei4
  0 siblings, 0 replies; 3+ messages in thread
From: zwei4 @ 2017-05-11  2:24 UTC (permalink / raw)
  To: edk2-devel

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
---
 .../Cpu/Include/Private/Library/CpuS3Lib.h         |   4 +-
 .../Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c  |   6 +-
 .../PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c        |   4 +-
 .../Cpu/Library/Private/PeiCpuS3Lib/CpuS3Lib.c     |   4 +-
 .../Library/Private/PeiMpServiceLib/Microcode.c    |   5 +-
 .../Library/Private/PeiMpServiceLib/MpService.c    |  16 +--
 .../BroxtonSiPkg/Include/Library/PmcIpcLib.h       |  10 +-
 .../Private/Library/CseVariableStorageLib.h        |  34 +++---
 .../Library/CseVariableStorageSelectorLib.h        |   8 +-
 .../BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c    |   5 +-
 .../BaseCseVariableStorageLib.c                    |  34 +++---
 .../CseVariableStorageSelectorLib.c                |   6 +-
 .../PeiCseVariableStorageSelectorLib.c             |   6 +-
 .../Library/DxeSmbiosMemoryLib/SmbiosMemory.h      |   6 +-
 .../Library/DxeSmbiosMemoryLib/SmbiosType16.c      |   5 +-
 .../NorthCluster/PciHostBridge/Dxe/PciHostBridge.c |  41 ++++---
 .../NorthCluster/SaInit/Dxe/IgdOpRegion.c          |   4 +-
 .../MdeModulePkg/Include/Ppi/SmmControl.h          |   4 +-
 .../PeiDxeSmmPchSerialIoLib.c                      |   8 +-
 .../PeiDxeSmmPchSerialIoLib.inf                    |   4 -
 .../SouthCluster/ScSmiDispatcher/Smm/ScSmmCore.c   | 120 ++++++++++++---------
 .../SouthCluster/ScSmiDispatcher/Smm/ScSmmGpi.c    |   6 +-
 .../SouthCluster/ScSmiDispatcher/Smm/ScSmmIchn.c   |  26 ++---
 .../ScSmiDispatcher/Smm/ScSmmPeriodicTimer.c       |  10 +-
 .../ScSmiDispatcher/Smm/ScSmmPowerButton.c         |   6 +-
 .../SouthCluster/ScSmiDispatcher/Smm/ScSmmSw.c     |   6 +-
 .../SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c     |   6 +-
 .../SouthCluster/ScSmiDispatcher/Smm/ScSmmUsb.c    |  10 +-
 .../Sdio/Dxe/MMC/MmcMediaDeviceDxe/MMCSDTransfer.c |   1 +
 .../Sdio/Dxe/SD/SdControllerDxe/SdController.c     |   3 +-
 .../BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c |   4 +-
 .../BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c |  24 ++---
 .../BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c  |  22 ++--
 .../Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.c      |   4 +-
 .../Library/Private/PeiDxeHeciInitLib/HeciCore.c   |  12 +--
 .../Txe/Library/Private/PeiSeCUma/SeCUma.c         |  12 +--
 .../SmmHeci2PowerManagementLib.c                   |   4 +-
 37 files changed, 256 insertions(+), 234 deletions(-)

diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Private/Library/CpuS3Lib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Private/Library/CpuS3Lib.h
index 48b4ac574..54e0e5bb2 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Private/Library/CpuS3Lib.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Include/Private/Library/CpuS3Lib.h
@@ -1,7 +1,7 @@
 /** @file
   Header file for Cpu Init Lib Pei Phase.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -27,7 +27,7 @@
 **/
 EFI_STATUS
 S3InitializeCpu (
-  IN CONST EFI_PEI_SERVICES    **PeiServices
+  IN  EFI_PEI_SERVICES    **PeiServices
   );
 #endif
 
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
index 1b67c9813..a645e17a9 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c
@@ -1,7 +1,7 @@
 /** @file
   This file is PeiCpuPolicy library.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -27,9 +27,7 @@ LoadCpuPreMemDefault (
   IN   VOID         *ConfigBlockPointer
   )
 {
-  CPU_CONFIG_PREMEM    *CpuConfigPreMem;
 
-  CpuConfigPreMem = ConfigBlockPointer;
 
   return EFI_SUCCESS;
 }
@@ -41,9 +39,7 @@ LoadBiosGuardDefault (
   IN   VOID         *ConfigBlockPointer
   )
 {
-  BIOS_GUARD_CONFIG  *BiosGuardConfig;
 
-  BiosGuardConfig = ConfigBlockPointer;
 
   return EFI_SUCCESS;
 }
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c
index 92e8a5520..edfdd10fb 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c
@@ -1,7 +1,7 @@
 /** @file
   This file is PeiCpuPolicy library.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -22,9 +22,7 @@ LoadCpuPreMemDefault (
   IN   VOID         *ConfigBlockPointer
   )
 {
-  CPU_CONFIG_PREMEM    *CpuConfigPreMem;
 
-  CpuConfigPreMem = ConfigBlockPointer;
 
   return EFI_SUCCESS;
 }
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiCpuS3Lib/CpuS3Lib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiCpuS3Lib/CpuS3Lib.c
index 8c4c8f34e..f5fde35db 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiCpuS3Lib/CpuS3Lib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiCpuS3Lib/CpuS3Lib.c
@@ -1,7 +1,7 @@
 /** @file
   Cpu S3 library running on S3 resume paths.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -561,7 +561,7 @@ RestoreSmramCpuData (
 **/
 EFI_STATUS
 S3InitializeCpu (
-  IN CONST EFI_PEI_SERVICES    **PeiServices
+  IN  EFI_PEI_SERVICES    **PeiServices
   )
 {
   EFI_STATUS              Status;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/Microcode.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/Microcode.c
index 1b4a0b581..f0c8dd90c 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/Microcode.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/Microcode.c
@@ -1,7 +1,7 @@
 /** @file
   CPU microcode update library.
 
-  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -194,11 +194,10 @@ InitializeMicrocode (
   EFI_STATUS          Status;
   EFI_CPUID_REGISTER  Cpuid;
   UINT32              UcodeRevision;
-  ACPI_CPU_DATA       *mAcpiCpuData;
 
   Status = EFI_NOT_FOUND;
 
-  mAcpiCpuData = (ACPI_CPU_DATA *) (ExchangeInfo->AcpiCpuDataAddress);
+
   AsmCpuid (
     CPUID_VERSION_INFO,
     &Cpuid.RegEax,
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/MpService.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/MpService.c
index 55e38c632..103ef2ac5 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/MpService.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/Library/Private/PeiMpServiceLib/MpService.c
@@ -1,7 +1,7 @@
 /** @file
   PEIM to initialize multi-processor.
 
-  Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -730,7 +730,7 @@ SwitchBsp (
   IN BOOLEAN                  EnableOldBsp
   )
 {
-  EFI_STATUS            Status;
+
   CPU_DATA_BLOCK        *CpuData;
   CPU_STATE             CpuState;
   UINT64                *MtrrValues;
@@ -804,7 +804,7 @@ SwitchBsp (
     }
   }
 
-  Status              = ChangeCpuState (mMpSystemData->BSP, EnableOldBsp, CPU_CAUSE_NOT_DISABLED);
+  ChangeCpuState (mMpSystemData->BSP, EnableOldBsp, CPU_CAUSE_NOT_DISABLED);
   mMpSystemData->BSP  = CpuNumber;
 
   return EFI_SUCCESS;
@@ -1004,7 +1004,7 @@ FillMpData (
   IN UINTN                MaximumCPUsForThisSystem
   )
 {
-  EFI_STATUS     Status;
+
   BOOLEAN        HyperThreadingEnabled;
 
   mMpSystemData = &mMpCpuRuntimeData->MpSystemData;
@@ -1025,10 +1025,10 @@ FillMpData (
   mMpCpuRuntimeData->AcpiCpuData.APState         = HyperThreadingEnabled;
   mMpCpuRuntimeData->AcpiCpuData.StackAddress    = (EFI_PHYSICAL_ADDRESS) (UINTN) StackAddressStart;
 
-  Status = PrepareGdtIdtForAP (
-             (IA32_DESCRIPTOR *) (UINTN) mMpCpuRuntimeData->AcpiCpuData.GdtrProfile,
-             (IA32_DESCRIPTOR *) (UINTN) mMpCpuRuntimeData->AcpiCpuData.IdtrProfile
-             );
+  PrepareGdtIdtForAP (
+    (IA32_DESCRIPTOR *) (UINTN) mMpCpuRuntimeData->AcpiCpuData.GdtrProfile,
+    (IA32_DESCRIPTOR *) (UINTN) mMpCpuRuntimeData->AcpiCpuData.IdtrProfile
+    );
 
   //
   // First BSP fills and inits all known values, including it's own records.
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h
index 905211bc7..923feca42 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Library/PmcIpcLib.h
@@ -1,7 +1,7 @@
 /** @file
   Base IPC library implementation.
 
-  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -169,7 +169,7 @@ typedef union {
   @retval  EFI_NOT_READY  Not ready for a new IPC
 
 **/
-RETURN_STATUS
+EFI_STATUS
 EFIAPI
 ReadyForNewIpc (
   VOID
@@ -182,7 +182,7 @@ ReadyForNewIpc (
   @param[in]   MessageId    The message identifier to send in the IPC packet.
 
 **/
-RETURN_STATUS
+EFI_STATUS
 EFIAPI
 IpcSendCommand (
   IN UINT32  MessageId
@@ -199,7 +199,7 @@ IpcSendCommand (
   @param[in, out] BufferSize                 The size, in bytes, of Buffer.  Ignored if Buffer is NULL.
 
 **/
-RETURN_STATUS
+EFI_STATUS
 EFIAPI
 IpcSendCommandEx (
   IN      UINT32  Command,
@@ -222,7 +222,7 @@ IpcSendCommandEx (
   @param[in, out] BufferSize                 The size, in bytes, of Buffer.  Ignored if Buffer is NULL.
 
 **/
-RETURN_STATUS
+EFI_STATUS
 EFIAPI
 IpcSendCommandBar0Ex (
   IN      UINT32  PciBar0,
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageLib.h
index 34100b83a..1a2a06eeb 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageLib.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageLib.h
@@ -1,7 +1,7 @@
 /** @file
   CSE Variable Storage Library.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -131,11 +131,11 @@ InitializeCseStorageGlobalVariableStructures (
 EFI_STATUS
 EFIAPI
 GetNextCseVariableName (
-  IN   CHAR16                  *VariableName,
-  IN   EFI_GUID                *VariableGuid,
-  IN   CSE_VARIABLE_FILE_INFO  **CseVariableFileInfo,
-  OUT  VARIABLE_NVM_HEADER     **VariablePtr,
-  OUT  BOOLEAN                 *IsAuthVariable
+  IN   CONST CHAR16                  *VariableName,
+  IN   CONST EFI_GUID                *VariableGuid,
+  IN   CSE_VARIABLE_FILE_INFO        **CseVariableFileInfo,
+  OUT  VARIABLE_NVM_HEADER           **VariablePtr,
+  OUT  BOOLEAN                       *IsAuthVariable
   );
 
 /**
@@ -246,10 +246,10 @@ BuildCseDataFileName (
 EFI_STATUS
 EFIAPI
 FindVariable (
-  IN  CONST  CHAR16                      *VariableName,
-  IN  CONST  EFI_GUID                    *VendorGuid,
-  IN  CONST  CSE_VARIABLE_FILE_INFO      **CseVariableFileInfo,
-  OUT        VARIABLE_NVM_POINTER_TRACK  *VariablePtrTrack
+  IN   CONST  CHAR16                      *VariableName,
+  IN   CONST  EFI_GUID                    *VendorGuid,
+  IN   CSE_VARIABLE_FILE_INFO             **CseVariableFileInfo,
+  OUT  VARIABLE_NVM_POINTER_TRACK         *VariablePtrTrack
   );
 
 /**
@@ -312,13 +312,13 @@ FindDeletedVariable (
 EFI_STATUS
 EFIAPI
 GetCseVariable (
-  IN CONST  CSE_VARIABLE_FILE_INFO     **CseVariableFileInfo,
-  IN CONST  CHAR16                     *VariableName,
-  IN CONST  EFI_GUID                   *VariableGuid,
-  OUT       UINT32                     *Attributes            OPTIONAL,
-  IN OUT    UINTN                      *DataSize,
-  OUT       VOID                       *Data,
-  OUT       VARIABLE_NVM_HEADER        *VariableHeader        OPTIONAL
+  IN         CSE_VARIABLE_FILE_INFO     **CseVariableFileInfo,
+  IN  CONST  CHAR16                     *VariableName,
+  IN  CONST  EFI_GUID                   *VariableGuid,
+  OUT        UINT32                     *Attributes            OPTIONAL,
+  IN OUT     UINTN                      *DataSize,
+  OUT        VOID                       *Data,
+  OUT        VARIABLE_NVM_HEADER        *VariableHeader        OPTIONAL
   );
 
 #endif
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageSelectorLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageSelectorLib.h
index f1b5cb201..141728083 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageSelectorLib.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Include/Private/Library/CseVariableStorageSelectorLib.h
@@ -1,7 +1,7 @@
 /** @file
   CSE Variable Storage Selector Library.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -46,9 +46,9 @@ typedef enum {
 CSE_VARIABLE_FILE_TYPE
 EFIAPI
 GetCseVariableStoreFileType (
-  IN CONST CHAR16                 *VariableName,
-  IN CONST EFI_GUID               *VendorGuid,
-  IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo
+  IN  CONST CHAR16                 *VariableName,
+  IN  CONST EFI_GUID               *VendorGuid,
+  IN  CSE_VARIABLE_FILE_INFO       **CseVariableFileInfo
   );
 
 /**
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c
index 48e037bd9..77aaa85ec 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/BaseIpcLib.c
@@ -1,7 +1,7 @@
 /** @file
   Base IPC library implementation.
 
-  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -66,6 +66,7 @@ ReadyForNewIpc (
 
 **/
 EFI_STATUS
+EFIAPI
 IpcSendCommandEx (
   IN      UINT32  Command,
   IN      UINT8   SubCommand,
@@ -108,7 +109,7 @@ IpcSendCommandEx (
   @param[in, out] BufferSize            The size, in bytes, of Buffer.  Ignored if Buffer is NULL.
 
 **/
-RETURN_STATUS
+EFI_STATUS
 EFIAPI
 IpcSendCommandBar0Ex (
   IN      UINT32  PciBar0,
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/BaseCseVariableStorageLib/BaseCseVariableStorageLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/BaseCseVariableStorageLib/BaseCseVariableStorageLib.c
index f60ed52ab..936495394 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/BaseCseVariableStorageLib/BaseCseVariableStorageLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/BaseCseVariableStorageLib/BaseCseVariableStorageLib.c
@@ -1,7 +1,7 @@
 /** @file
   CSE Variable Storage Library.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016-2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -110,7 +110,7 @@ EstablishAndLoadCseVariableStores (
         //
         // Check if the variable store exists
         //
-        Status = HeciGetNVMFileSize (CseVariableFileInfo[Type]->FileName, &VariableHeaderRegionBufferSize);
+        Status = HeciGetNVMFileSize ((UINT8 *)(CseVariableFileInfo[Type]->FileName), &VariableHeaderRegionBufferSize);
 
         //
         // If there's an error finding the file, do not establish this store as
@@ -354,9 +354,9 @@ ReadCseNvmFile (
   }
 
   if (HeciProtocolActive == CseVariableHeci1Protocol) {
-    return HeciReadNVMFile (CseFileName, FileOffset, Data, DataSize);
+    return HeciReadNVMFile ((UINT8 *)CseFileName, FileOffset, Data, DataSize);
   } else if (Heci2Protocol != NULL) {
-    return Heci2ReadNVMFile (CseFileName, FileOffset, Data, DataSize, Heci2Protocol);
+    return Heci2ReadNVMFile ((UINT8 *)CseFileName, FileOffset, Data, DataSize, Heci2Protocol);
   } else {
     ASSERT (FALSE);
   }
@@ -412,9 +412,9 @@ UpdateCseNvmFile (
   }
 
   if (HeciProtocolActive == CseVariableHeci1Protocol) {
-    return HeciWriteNVMFile (CseFileName, FileOffset, Data, DataSize, Truncate);
+    return HeciWriteNVMFile ((UINT8 *)CseFileName, FileOffset, Data, DataSize, Truncate);
   } else if (Heci2Protocol != NULL) {
-    Status = Heci2WriteNVMFile (CseFileName, FileOffset, Data, DataSize, Truncate);
+    Status = Heci2WriteNVMFile ((UINT8 *)CseFileName, FileOffset, Data, DataSize, Truncate);
     return Status;
   } else {
     ASSERT (FALSE);
@@ -455,7 +455,7 @@ CreateCseNvmVariableStore (
   //
   // Check if a variable store already exists
   //
-  Status = HeciGetNVMFileSize (StoreFileName, StoreSize);
+  Status = HeciGetNVMFileSize ((UINT8 *)StoreFileName, StoreSize);
   if (Status == EFI_SUCCESS || (Status != EFI_NOT_FOUND && EFI_ERROR (Status))) {
     return Status;
   }
@@ -731,10 +731,10 @@ FindVariableEx (
 EFI_STATUS
 EFIAPI
 FindVariable (
-  IN  CONST  CHAR16                      *VariableName,
-  IN  CONST  EFI_GUID                    *VendorGuid,
-  IN  CONST  CSE_VARIABLE_FILE_INFO      **CseVariableFileInfo,
-  OUT        VARIABLE_NVM_POINTER_TRACK  *VariablePtrTrack
+  IN   CONST CHAR16                      *VariableName,
+  IN   CONST EFI_GUID                    *VendorGuid,
+  IN    CSE_VARIABLE_FILE_INFO      **CseVariableFileInfo,
+  OUT   VARIABLE_NVM_POINTER_TRACK  *VariablePtrTrack
   )
 {
   EFI_STATUS                  Status;
@@ -801,9 +801,9 @@ FindVariable (
 EFI_STATUS
 EFIAPI
 GetNextCseVariableName (
-  IN   CHAR16                  *VariableName,
-  IN   EFI_GUID                *VariableGuid,
-  IN   CSE_VARIABLE_FILE_INFO  **CseVariableFileInfo,
+  IN  CONST CHAR16                  *VariableName,
+  IN  CONST EFI_GUID                *VariableGuid,
+  IN    CSE_VARIABLE_FILE_INFO  **CseVariableFileInfo,
   OUT  VARIABLE_NVM_HEADER     **VariablePtr,
   OUT  BOOLEAN                 *IsAuthVariable
   )
@@ -979,9 +979,9 @@ GetNextCseVariableName (
 EFI_STATUS
 EFIAPI
 GetCseVariable (
-  IN CONST  CSE_VARIABLE_FILE_INFO     **CseVariableFileInfo,
-  IN CONST  CHAR16                     *VariableName,
-  IN CONST  EFI_GUID                   *VariableGuid,
+  IN        CSE_VARIABLE_FILE_INFO     **CseVariableFileInfo,
+  IN  CONST      CHAR16                     *VariableName,
+  IN  CONST      EFI_GUID                   *VariableGuid,
   OUT       UINT32                     *Attributes            OPTIONAL,
   IN OUT    UINTN                      *DataSize,
   OUT       VOID                       *Data,
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStorageSelectorLib/CseVariableStorageSelectorLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStorageSelectorLib/CseVariableStorageSelectorLib.c
index 108719615..be65bd8a1 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStorageSelectorLib/CseVariableStorageSelectorLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStorageSelectorLib/CseVariableStorageSelectorLib.c
@@ -31,9 +31,9 @@ EFI_HECI_PROTOCOL *mHeci2Protocol = NULL;
 CSE_VARIABLE_FILE_TYPE
 EFIAPI
 GetCseVariableStoreFileType (
-  IN CONST CHAR16                 *VariableName,
-  IN CONST EFI_GUID               *VendorGuid,
-  IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo
+  IN  CONST CHAR16                 *VariableName,
+  IN  CONST EFI_GUID               *VendorGuid,
+  IN  CSE_VARIABLE_FILE_INFO       **CseVariableFileInfo
   )
 {
   CSE_VARIABLE_FILE_TYPE  Type;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorageSelectorLib/PeiCseVariableStorageSelectorLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorageSelectorLib/PeiCseVariableStorageSelectorLib.c
index a9d93fe68..f2caaa4f5 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorageSelectorLib/PeiCseVariableStorageSelectorLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorageSelectorLib/PeiCseVariableStorageSelectorLib.c
@@ -32,9 +32,9 @@
 CSE_VARIABLE_FILE_TYPE
 EFIAPI
 GetCseVariableStoreFileType (
-  IN CONST CHAR16                 *VariableName,
-  IN CONST EFI_GUID               *VendorGuid,
-  IN CONST CSE_VARIABLE_FILE_INFO **CseVariableFileInfo
+  IN  CONST CHAR16                 *VariableName,
+  IN  CONST EFI_GUID               *VendorGuid,
+  IN  CSE_VARIABLE_FILE_INFO       **CseVariableFileInfo
   )
 {
   CSE_VARIABLE_FILE_TYPE    Type;
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosMemory.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosMemory.h
index b62cd67e6..4effcd33b 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosMemory.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosMemory.h
@@ -3,7 +3,7 @@
   This driver will determine memory configuration information from the chipset
   and memory and create SMBIOS memory structures appropriately.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -159,9 +159,9 @@ typedef struct {
 //
 // Module-wide global variables
 //
-MEM_INFO_PROTOCOL               *mMemInfoHob;
+extern MEM_INFO_PROTOCOL               *mMemInfoHob;
 extern EFI_SMBIOS_PROTOCOL       *mSmbios;
-EFI_SMBIOS_HANDLE      mSmbiosType16Handle;
+extern EFI_SMBIOS_HANDLE      mSmbiosType16Handle;
 
 extern CHAR8 *DimmToDevLocator[];
 extern CHAR8 *DimmToBankLocator[];
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c
index 2124543b1..194df4494 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c
@@ -2,7 +2,7 @@
   This library will determine memory configuration information from the chipset
   and memory and create SMBIOS memory structures appropriately.
 
-  Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -16,6 +16,9 @@
 
 #include "SmbiosMemory.h"
 
+MEM_INFO_PROTOCOL      *mMemInfoHob;
+EFI_SMBIOS_HANDLE      mSmbiosType16Handle;
+
 //
 // Physical Memory Array (Type 16) data
 //
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.c
index 834cace03..3f7a51d27 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/PciHostBridge/Dxe/PciHostBridge.c
@@ -2,7 +2,7 @@
   Pci Host Bridge driver:
   Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation.
 
-  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -41,24 +41,37 @@
 //
 static UINTN                              RootBridgeNumber[1]       = { 1 };
 
-static UINT64                             RootBridgeAttribute[1][1] = { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM };
+static UINT64                             RootBridgeAttribute[1][1] = { {EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM }};
 
 static EFI_PCI_ROOT_BRIDGE_DEVICE_PATH    mEfiPciRootBridgeDevicePath[1][1] = {
-  {
-    ACPI_DEVICE_PATH,
-    ACPI_DP,
-    (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),
-    (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8),
-    EISA_PNP_ID(0x0A03),
-    0,
-    END_DEVICE_PATH_TYPE,
-    END_ENTIRE_DEVICE_PATH_SUBTYPE,
-    END_DEVICE_PATH_LENGTH,
-    0
+{ 
+ {
+    {
+      {
+        ACPI_DEVICE_PATH,
+        ACPI_DP,
+        {
+          (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),
+          (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)
+        }
+       },
+       EISA_PNP_ID(0x0A03),
+       0
+    },
+    {
+      END_DEVICE_PATH_TYPE,
+      END_ENTIRE_DEVICE_PATH_SUBTYPE,
+      {
+        END_DEVICE_PATH_LENGTH,
+        0
+      }
+    }
   }
+
+ }
 };
 
-static PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[1][1] = { { 0, 255, 0, 0xffffffff, 0, 1 << 16 } };
+static PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[1][1] = { {{ 0, 255, 0, 0xffffffff, 0, (1 << 16) } }};
 
 static EFI_HANDLE                         mDriverImageHandle;
 
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/SaInit/Dxe/IgdOpRegion.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/SaInit/Dxe/IgdOpRegion.c
index 961c6b2a0..5d147879a 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/SaInit/Dxe/IgdOpRegion.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/SaInit/Dxe/IgdOpRegion.c
@@ -3,7 +3,7 @@
   Software SCI interface between system BIOS, ASL code, and Graphics drivers.
   The code in this file will load the driver and initialize the interface.
 
-  Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -722,7 +722,7 @@ IgdOpRegionInit (
   //
   Status = EfiCreateEventReadyToBootEx(
              TPL_CALLBACK,
-             SetGOPVersionCallback,
+             (EFI_EVENT_NOTIFY)SetGOPVersionCallback,
              NULL,
              &mReadyToBootEvent
              );
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Include/Ppi/SmmControl.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Include/Ppi/SmmControl.h
index e7b67c5a6..7dd71a530 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Include/Ppi/SmmControl.h
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SampleCode/MdeModulePkg/Include/Ppi/SmmControl.h
@@ -9,7 +9,7 @@
   event from a platform chipset agent is an optional capability for both IA-32 and Itanium-based
   systems.
 
-  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -25,7 +25,7 @@
 #define _SMM_CONTROL_PPI_H_
 
 #define PEI_SMM_CONTROL_PPI_GUID \
-  { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }
+  { 0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5} }
 
 typedef struct _PEI_SMM_CONTROL_PPI  PEI_SMM_CONTROL_PPI;
 
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c
index 36dcf53d1..209d6493d 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.c
@@ -3,7 +3,7 @@
   All function in this library is available for PEI, DXE, and SMM,
   But do not support UEFI RUNTIME environment call.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -214,7 +214,7 @@ ConfigureSerialIoController (
         Bar = MmioRead32 (PciCfgBase + R_LPSS_IO_BAR) & 0xFFFFF000;
       }
 
-      MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, Bar);
+      MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, (UINT32)Bar);
 
       //
       // Set Memory space Enable
@@ -236,7 +236,7 @@ ConfigureSerialIoController (
 
         do {
           PchPcrRead32(0xC6, SerialIoPsf3Offsets[Controller].Psf3BaseAddress + 0x001C, &Data32);
-        } while (Data32 & BIT18 != BIT18);
+        } while ((Data32 & BIT18) != BIT18);
 
         //
         // Assign BAR0 and Set Memory space Enable
@@ -254,7 +254,7 @@ ConfigureSerialIoController (
       //
       // Update Address Remap Register with Current BAR
       //
-      MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, Bar);
+      MmioWrite32 (Bar + R_LPSS_IO_REMAP_ADDRESS_LOW, (UINT32)Bar);
 
       ///
       /// Get controller out of reset
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf
index 2e8b9b5bf..da4f849a1 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLib.inf
@@ -35,7 +35,3 @@
   MmPciLib
   ScPlatformLib
 
-[BuildOptions]
-  *_*_IA32_ASM_FLAGS = /w /Od /GL-
-  *_*_IA32_CC_FLAGS = /w /Od /GL-
-  *_*_X64_CC_FLAGS = /w /Od /GL-
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmCore.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmCore.c
index c9a956677..2886a849e 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmCore.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmCore.c
@@ -2,7 +2,7 @@
   This driver is responsible for the registration of child drivers
   and the abstraction of the SC SMI sources.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -33,84 +33,102 @@ PRIVATE_DATA          mPrivateData = {  // for the structure
   NULL,                                 // Handler returned whan calling SmiHandlerRegister
   NULL,                                 // EFI handle returned when calling InstallMultipleProtocolInterfaces
   {                                     // protocol arrays
+
+    {
     //
     // elements within the array
     //
-    {
-      PROTOCOL_SIGNATURE,
-      UsbType,
-      &gEfiSmmUsbDispatch2ProtocolGuid,
-      {
-        (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
-        (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister
-      }
+        (UINTN)PROTOCOL_SIGNATURE,
+        UsbType,
+        &gEfiSmmUsbDispatch2ProtocolGuid,
+        {
+         {
+          (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
+          (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister
+         }
+        }
+
     },
     {
-      PROTOCOL_SIGNATURE,
-      SxType,
-      &gEfiSmmSxDispatch2ProtocolGuid,
-      {
-        (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
-        (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister
-      }
+
+        (UINTN)PROTOCOL_SIGNATURE,
+        SxType,
+        &gEfiSmmSxDispatch2ProtocolGuid,
+        {{
+          (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
+          (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister
+        }}
+      
     },
     {
-      PROTOCOL_SIGNATURE,
-      SwType,
-      &gEfiSmmSwDispatch2ProtocolGuid,
-      {
-        (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
-        (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister,
-        (UINTN) MAXIMUM_SWI_VALUE
-      }
+
+        (UINTN)PROTOCOL_SIGNATURE,
+        SwType,
+        &gEfiSmmSwDispatch2ProtocolGuid,
+        {{
+          (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
+          (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister,
+          (UINTN) MAXIMUM_SWI_VALUE
+        }}
+      
     },
     {
-      PROTOCOL_SIGNATURE,
-      GpiType,
-      &gEfiSmmGpiDispatch2ProtocolGuid,
-      {
-        (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
-        (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister,
-        (UINTN) V_GPIO_NUM_SUPPORTED_GPIS
-      }
+
+        (UINTN)PROTOCOL_SIGNATURE,
+        GpiType,
+        &gEfiSmmGpiDispatch2ProtocolGuid,
+        {{
+          (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
+          (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister,
+          (UINTN) V_GPIO_NUM_SUPPORTED_GPIS
+        }}
+
     },
     {
-      PROTOCOL_SIGNATURE,
-      IchnType,
-      &gEfiSmmIchnDispatchProtocolGuid,
-      {
-        (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
-        (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister
-      }
+
+        (UINTN)PROTOCOL_SIGNATURE,
+        IchnType,
+        &gEfiSmmIchnDispatchProtocolGuid,
+        {{
+          (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
+          (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister
+        }}
+
     },
-    {
-      PROTOCOL_SIGNATURE,
+    { 
+
+      (UINTN)PROTOCOL_SIGNATURE,
       IchnExType,
       &gEfiSmmIchnDispatchExProtocolGuid,
-      {
+      {{
         (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
         (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister
-      }
+      }}
+
     },
-    {
-      PROTOCOL_SIGNATURE,
+    {  
+
+      (UINTN)PROTOCOL_SIGNATURE,
       PowerButtonType,
       &gEfiSmmPowerButtonDispatch2ProtocolGuid,
-      {
+      {{
         (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
         (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister
-      }
+      }}
+      
     },
     {
-      PROTOCOL_SIGNATURE,
+
+      (UINTN)PROTOCOL_SIGNATURE,
       PeriodicTimerType,
       &gEfiSmmPeriodicTimerDispatch2ProtocolGuid,
-      {
+      {{
         (SC_SMM_GENERIC_REGISTER) ScSmmCoreRegister,
         (SC_SMM_GENERIC_UNREGISTER) ScSmmCoreUnRegister,
         (UINTN) ScSmmPeriodicTimerDispatchGetNextShorterInterval
-      }
-    },
+      }}
+
+    }
   }
 };
 
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmGpi.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmGpi.c
index 195288edf..090db445f 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmGpi.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmGpi.c
@@ -1,7 +1,7 @@
 /** @file
   File to contain all the hardware specific stuff for the Smm Gpi dispatch protocol.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -26,7 +26,7 @@ CONST SC_SMM_SOURCE_DESC  SC_GPI_SOURCE_DESC_TEMPLATE = {
   {
     {
       {
-        GPIO_ADDR_TYPE, 0x0
+        GPIO_ADDR_TYPE, {0x0}
       },
       S_GPIO_GP_SMI_EN, 0x0,
     },
@@ -36,7 +36,7 @@ CONST SC_SMM_SOURCE_DESC  SC_GPI_SOURCE_DESC_TEMPLATE = {
   {
     {
       {
-        GPIO_ADDR_TYPE, 0x0
+        GPIO_ADDR_TYPE, {0x0}
       },
       S_GPIO_GP_SMI_STS, 0x0,
     },
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmIchn.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmIchn.c
index aeb3b1538..b2b58edb8 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmIchn.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmIchn.c
@@ -1,7 +1,7 @@
 /** @file
   File to contain all the hardware specific stuff for the Smm Ichn dispatch protocol.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -56,7 +56,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_ACPI_PM1_EN
+          {R_ACPI_PM1_EN}
         },
         S_ACPI_PM1_EN,
         N_ACPI_PM1_EN_RTC
@@ -68,7 +68,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_ACPI_PM1_STS
+          {R_ACPI_PM1_STS}
         },
         S_ACPI_PM1_STS,
         N_ACPI_PM1_STS_RTC
@@ -122,7 +122,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_STS
+          {R_SMI_STS}
         },
         S_SMI_STS,
         N_SMI_STS_SERIRQ
@@ -154,7 +154,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_EN
+          {R_SMI_EN}
         },
         S_SMI_EN,
         N_SMI_EN_TCO
@@ -166,7 +166,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_STS
+          {R_SMI_STS}
         },
         S_SMI_STS,
         N_SMI_STS_TCO
@@ -198,7 +198,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_EN
+          {R_SMI_EN}
         },
         S_SMI_EN,
         N_SMI_EN_TCO
@@ -207,7 +207,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           PCR_ADDR_TYPE,
-          SC_PCR_ADDRESS (0xD0, R_PCR_ITSS_NMICSTS)
+          {SC_PCR_ADDRESS (0xD0, R_PCR_ITSS_NMICSTS)}
         },
         S_PCR_ITSS_NMICSTS,
         N_PCR_ITSS_NMI2SMIEN
@@ -218,7 +218,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           PCR_ADDR_TYPE,
-          SC_PCR_ADDRESS (0xD0, R_PCR_ITSS_NMICSTS)
+          {SC_PCR_ADDRESS (0xD0, R_PCR_ITSS_NMICSTS)}
         },
         S_PCR_ITSS_NMICSTS,
         N_PCR_ITSS_NMI2SMISTS
@@ -251,7 +251,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_EN
+          {R_SMI_EN}
         },
         S_SMI_EN,
         N_SMI_EN_SPI_SSMI
@@ -276,7 +276,7 @@ SC_SMM_SOURCE_DESC ICHN_SOURCE_DESCS[NUM_ICHN_TYPES] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_STS
+          {R_SMI_STS}
         },
         S_SMI_STS,
         N_SMI_STS_SPI_SSMI
@@ -474,7 +474,7 @@ SC_SMM_SOURCE_DESC ICHN_EX_SOURCE_DESCS[IchnExTypeMAX - IchnExPciExpress] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_ACPI_PM1_EN
+          {R_ACPI_PM1_EN}
         },
         S_ACPI_PM1_EN,
         N_ACPI_PM1_EN_TMROF
@@ -486,7 +486,7 @@ SC_SMM_SOURCE_DESC ICHN_EX_SOURCE_DESCS[IchnExTypeMAX - IchnExPciExpress] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_ACPI_PM1_STS
+          {R_ACPI_PM1_STS}
         },
         S_ACPI_PM1_STS,
         N_ACPI_PM1_STS_TMROF
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmPeriodicTimer.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmPeriodicTimer.c
index a7d69fa7e..c752e2e4e 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmPeriodicTimer.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmPeriodicTimer.c
@@ -1,7 +1,7 @@
 /** @file
   File to contain all the hardware specific stuff for the Periodical Timer dispatch protocol.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -115,7 +115,7 @@ SC_SMM_SOURCE_DESC mTIMER_SOURCE_DESCS[NUM_TIMERS] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_EN
+          {R_SMI_EN}
         },
         S_SMI_EN,
         N_SMI_EN_PERIODIC
@@ -127,7 +127,7 @@ SC_SMM_SOURCE_DESC mTIMER_SOURCE_DESCS[NUM_TIMERS] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_STS
+          {R_SMI_STS}
         },
         S_SMI_STS,
         N_SMI_STS_PERIODIC
@@ -141,7 +141,7 @@ SC_SMM_SOURCE_DESC mTIMER_SOURCE_DESCS[NUM_TIMERS] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_EN
+          {R_SMI_EN}
         },
         S_SMI_EN,
         N_SMI_EN_SWSMI_TMR
@@ -153,7 +153,7 @@ SC_SMM_SOURCE_DESC mTIMER_SOURCE_DESCS[NUM_TIMERS] = {
       {
         {
           ACPI_ADDR_TYPE,
-          R_SMI_STS
+          {R_SMI_STS}
         },
         S_SMI_STS,
         N_SMI_STS_SWSMI_TMR
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmPowerButton.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmPowerButton.c
index 497ca74a1..166658fa5 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmPowerButton.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmPowerButton.c
@@ -1,7 +1,7 @@
 /** @file
   File to contain all the hardware specific stuff for the Smm Power Button dispatch protocol.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -21,7 +21,7 @@ CONST SC_SMM_SOURCE_DESC POWER_BUTTON_SOURCE_DESC = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_ACPI_PM1_EN
+        {R_ACPI_PM1_EN}
       },
       S_ACPI_PM1_EN,
       N_ACPI_PM1_EN_PWRBTN
@@ -33,7 +33,7 @@ CONST SC_SMM_SOURCE_DESC POWER_BUTTON_SOURCE_DESC = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_ACPI_PM1_STS
+        {R_ACPI_PM1_STS}
       },
       S_ACPI_PM1_STS,
       N_ACPI_PM1_STS_PWRBTN
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSw.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSw.c
index dab2309fc..8cdaae153 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSw.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSw.c
@@ -1,7 +1,7 @@
 /** @file
   File to contain all the hardware specific stuff for the Smm Sw dispatch protocol.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -30,7 +30,7 @@ CONST SC_SMM_SOURCE_DESC SW_SOURCE_DESC = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_SMI_EN
+        {R_SMI_EN}
       },
       S_SMI_EN,
       N_SMI_EN_APMC
@@ -42,7 +42,7 @@ CONST SC_SMM_SOURCE_DESC SW_SOURCE_DESC = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_SMI_STS
+        {R_SMI_STS}
       },
       S_SMI_STS,
       N_SMI_STS_APM
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c
index e1aa7fdcd..8baf1c0eb 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmSx.c
@@ -1,7 +1,7 @@
 /** @file
   File to contain all the hardware specific stuff for the Smm Sx dispatch protocol.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -25,7 +25,7 @@ const SC_SMM_SOURCE_DESC SX_SOURCE_DESC = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_SMI_EN
+        {R_SMI_EN}
       },
       S_SMI_EN,
       N_SMI_EN_ON_SLP_EN
@@ -37,7 +37,7 @@ const SC_SMM_SOURCE_DESC SX_SOURCE_DESC = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_SMI_STS
+        {R_SMI_STS}
       },
       S_SMI_STS,
       N_SMI_STS_ON_SLP_EN
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmUsb.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmUsb.c
index ea512121e..c514f42dc 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmUsb.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScSmiDispatcher/Smm/ScSmmUsb.c
@@ -1,7 +1,7 @@
 /** @file
   File to contain all the hardware specific stuff for the Smm USB dispatch protocol.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -22,7 +22,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED SC_SMM_SOURCE_DESC mUSB1_LEGACY = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_SMI_EN
+        {R_SMI_EN}
       },
       S_SMI_EN,
       N_SMI_EN_LEGACY_USB
@@ -34,7 +34,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED SC_SMM_SOURCE_DESC mUSB1_LEGACY = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_SMI_STS
+        {R_SMI_STS}
       },
       S_SMI_STS,
       N_SMI_STS_LEGACY_USB
@@ -48,7 +48,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED SC_SMM_SOURCE_DESC mUSB3_LEGACY = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_SMI_EN
+        {R_SMI_EN}
       },
       S_SMI_EN,
       N_SMI_EN_LEGACY_USB3
@@ -60,7 +60,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED SC_SMM_SOURCE_DESC mUSB3_LEGACY = {
     {
       {
         ACPI_ADDR_TYPE,
-        R_SMI_STS
+        {R_SMI_STS}
       },
       S_SMI_STS,
       N_SMI_STS_LEGACY_USB3
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MMCSDTransfer.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MMCSDTransfer.c
index d367326c1..13258dec0 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MMCSDTransfer.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/MMC/MmcMediaDeviceDxe/MMCSDTransfer.c
@@ -2244,6 +2244,7 @@ MmcGetCurrentPartitionNum (
 
 **/
 VOID
+EFIAPI
 SetEmmcWpOnEvent(
   IN EFI_EVENT          Event,
   IN VOID               *Context
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/SD/SdControllerDxe/SdController.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/SD/SdControllerDxe/SdController.c
index ff01c85e1..f4811969e 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/SD/SdControllerDxe/SdController.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Sdio/Dxe/SD/SdControllerDxe/SdController.c
@@ -1,7 +1,7 @@
 /** @file
   The SD host controller driver model and HC protocol routines.
 
-  Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -247,6 +247,7 @@ GetErrorReason (
 
 **/
 EFI_STATUS
+EFIAPI
 SetHighSpeedMode (
   IN  EFI_SD_HOST_IO_PROTOCOL    *This,
   IN  BOOLEAN                    Enable
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c
index bb98ae04b..3c114246c 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Dxe/Hecidrv.c
@@ -1,7 +1,7 @@
 /** @file
   HECI driver.
 
-  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -76,7 +76,7 @@ FlashDeviceEndOfPostEvent (
     Status = gBS->LocateProtocol (
                     &gEfiHeciSmmRuntimeProtocolGuid,
                     NULL,
-                    &mHeci2Protocol
+                    (VOID **)&mHeci2Protocol
                     );
     if (GetFirstGuidHob (&gFdoModeEnabledHobGuid) == NULL) {
       ASSERT_EFI_ERROR (Status);
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
index 0353ba701..c95cf0195 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmm.c
@@ -1,7 +1,7 @@
 /** @file
   HECI Smm driver.
 
-  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -22,7 +22,7 @@
 #include <HeciSmm.h>
 #include <Private/Library/HeciInitLib.h>
 #include <SeCAccess.h>
-#include <library/PciLib.h>
+#include <Library/PciLib.h>
 #include <Library/BaseMemoryLib.h>
 #include <Library/BaseLib.h>
 #include <Library/TimerLib.h>
@@ -1217,15 +1217,15 @@ AtRuntime (
 
 
 EFI_HECI_PROTOCOL mHeciSmmProtocol = {
-  EfiHeciSendwack,
-  EfiHeciReadMessage,
-  EfiHeciSendMessage,
-  EfiHeciReset,
-  EfiHeciInit,
-  EfiHeciResetWait,
-  EfiHeciReinit,
-  EfiHeciGetSecStatus,
-  EfiHeciGetSecMode
+  (EFI_HECI_SENDWACK)EfiHeciSendwack,
+  (EFI_HECI_READ_MESSAGE)EfiHeciReadMessage,
+  (EFI_HECI_SEND_MESSAGE)EfiHeciSendMessage,
+  (EFI_HECI_RESET)EfiHeciReset,
+  (EFI_HECI_INIT)EfiHeciInit,
+  (EFI_HECI_RESET_WAIT)EfiHeciResetWait,
+  (EFI_HECI_REINIT)EfiHeciReinit,
+  (EFI_HECI_GET_SEC_STATUS)EfiHeciGetSecStatus,
+  (EFI_HECI_GET_SEC_MODE)EfiHeciGetSecMode
 };
 
 EFI_HECI2_PM_PROTOCOL mHeci2PmSmmProtocol = {
@@ -1342,7 +1342,7 @@ HeciSmmInitialize (
   ASSERT_EFI_ERROR (Status);
 
   SmmHandle = NULL;
-  Status = gSmst->SmiHandlerRegister (SmmPlatformHeci2ProxyHandler, NULL, &SmmHandle);
+  Status = gSmst->SmiHandlerRegister ((EFI_SMM_HANDLER_ENTRY_POINT2)SmmPlatformHeci2ProxyHandler, NULL, &SmmHandle);
 
   //
   // Register EFI_SMM_END_OF_DXE_PROTOCOL_GUID notify function.
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c
index a23a1f48a..53184c414 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Heci/Smm/HeciSmmRuntimeDxe.c
@@ -1,7 +1,7 @@
 /** @file
   HECI Smm Runtime Dxe driver.
 
-  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -25,7 +25,7 @@
 #include <Library/UefiLib.h>
 #include <Library/BaseLib.h>
 #include <Guid/EventGroup.h>
-#include <protocol/Heci.h>
+#include <Protocol/Heci.h>
 #include <HeciSmm.h>
 #include <Library/SideBandLib.h>
 #include <SeCAccess.h>
@@ -523,15 +523,15 @@ EfiHeciGetSecMode (
 }
 
 EFI_HECI_PROTOCOL mHeciProtocol = {
-  EfiHeciSendwack,
-  EfiHeciReadMessage,
-  EfiHeciSendMessage,
-  EfiHeciReset,
-  EfiHeciInit,
-  EfiHeciResetWait,
-  EfiHeciReinit,
-  EfiHeciGetSecStatus,
-  EfiHeciGetSecMode
+  (EFI_HECI_SENDWACK)EfiHeciSendwack,
+  (EFI_HECI_READ_MESSAGE)EfiHeciReadMessage,
+  (EFI_HECI_SEND_MESSAGE)EfiHeciSendMessage,
+  (EFI_HECI_RESET)EfiHeciReset,
+  (EFI_HECI_INIT)EfiHeciInit,
+  (EFI_HECI_RESET_WAIT)EfiHeciResetWait,
+  (EFI_HECI_REINIT)EfiHeciReinit,
+  (EFI_HECI_GET_SEC_STATUS)EfiHeciGetSecStatus,
+  (EFI_HECI_GET_SEC_MODE)EfiHeciGetSecMode
 };
 
 
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.c
index f64f50ad5..2fd56f891 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/HeciMsgLib/DxeSmmHeciMsgLib.c
@@ -236,7 +236,7 @@ Heci2WriteNVMFile (
     //
     // Copy the name of the NVM file to write
     //
-    ASSERT (AsciiStrLen (FileName) <= sizeof (WriteFileMessage->FileName));
+    ASSERT (AsciiStrLen ((CONST CHAR8*)FileName) <= sizeof (WriteFileMessage->FileName));
     ASSERT (sizeof (Heci2DataBuffer) > sizeof (HECI2_TRUSTED_CHANNEL_BIOS_WRITE_REQ));
     AsciiStrCpyS ((CHAR8 *) WriteFileMessage->FileName, sizeof (WriteFileMessage->FileName), (CONST CHAR8 *) FileName);
 
@@ -351,7 +351,7 @@ Heci2ReadNVMFile (
     //
     // Copy the name of the NVM file to read
     //
-    ASSERT (AsciiStrLen (FileName) <= sizeof (ReadFileMessage->FileName));
+    ASSERT (AsciiStrLen ((CONST CHAR8*)FileName) <= sizeof (ReadFileMessage->FileName));
     ASSERT (sizeof (Heci2DataBuffer) > sizeof (HECI2_TRUSTED_CHANNEL_BIOS_READ_REQ));
     AsciiStrCpyS ((CHAR8 *) ReadFileMessage->FileName, sizeof (ReadFileMessage->FileName), (CONST CHAR8 *) FileName);
 
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiDxeHeciInitLib/HeciCore.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiDxeHeciInitLib/HeciCore.c
index 92934090d..50340eaba 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiDxeHeciInitLib/HeciCore.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiDxeHeciInitLib/HeciCore.c
@@ -1,7 +1,7 @@
 /** @file
   Heci driver core. For Dxe Phase, determines the HECI device and initializes it.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -528,7 +528,6 @@ HeciReceive (
 )
 {
   UINTN                                ReadSize;
-  UINTN                                Size;
   UINTN                                Index;
   UINTN                                HeciMBAR;
   HECI_MESSAGE_HEADER                  MessageHeader;
@@ -543,7 +542,7 @@ HeciReceive (
   EFI_STATUS                           Status;
 
   DEBUG ((EFI_D_INFO, "Start HeciReceive\n"));
-  Size = 0;
+
   ReadSize = 0;
 
   HeciMBAR = CheckAndFixHeciForAccess (HeciDev);
@@ -700,7 +699,7 @@ HeciSend (
   UINTN                  HeciMBAR;
   UINTN                  StallCount;
   UINTN                  MaxCount;
-  UINTN                  OverAllDelay;
+
   BOOLEAN                TimeOut;
   HECI_MESSAGE_HEADER    MessageHeader;
   EFI_HECI2_PM_PROTOCOL  *Heci2PmProtocol;
@@ -748,7 +747,7 @@ HeciSend (
   MaxBuffer = HostControlReg->r.H_CBD;
 
   MaxCount = 0;
-  OverAllDelay = 0;
+
   TimeOut = FALSE;
 
   DEBUG_CODE_BEGIN ();
@@ -961,11 +960,10 @@ HeciInitialize(
   HECI_FWS_REGISTER                   SeCFirmwareStatus;
   UINTN                               HeciMBAR;
   EFI_STATUS                          Status;
-  UINT32                              SeCMode;
+
 
   DEBUG ((EFI_D_INFO, "HECI Initialize  ++ \n "));
 
-  SeCMode = SEC_MODE_NORMAL;
 
   //
   // Make sure that HECI device BAR is correct and device is enabled.
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiSeCUma/SeCUma.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiSeCUma/SeCUma.c
index 06d1c260a..459ff4373 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiSeCUma/SeCUma.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/Private/PeiSeCUma/SeCUma.c
@@ -1,7 +1,7 @@
 /** @file
   Framework PEIM to SeCUma.
 
-  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -141,7 +141,6 @@ HandleSecBiosAction (
   IN UINT8                        BiosAction
   )
 {
-  EFI_STATUS              Status;
   HECI_FWS_REGISTER       SeCFirmwareStatus;
 
   //
@@ -163,7 +162,7 @@ HandleSecBiosAction (
       // Case: Perform Non-Power Cycle Reset
       //
       DEBUG ((DEBUG_ERROR, "SEC FW has requested a Non-PCR.\n"));
-      Status = PerformReset (CBM_DIR_NON_PCR);
+      PerformReset (CBM_DIR_NON_PCR);
       break;
 
     case CBM_DIR_PCR:
@@ -171,7 +170,7 @@ HandleSecBiosAction (
       // Case: Perform Power Cycle Reset
       //
       DEBUG ((DEBUG_ERROR, "SEC FW has requested a PCR.\n"));
-      Status = PerformReset (CBM_DIR_PCR);
+      PerformReset (CBM_DIR_PCR);
       break;
 
     case 3:
@@ -200,7 +199,7 @@ HandleSecBiosAction (
       // Case: Perform Global Reset
       //
       DEBUG ((DEBUG_ERROR, "SEC FW has requested a Global Reset.\n"));
-      Status = PerformReset (CBM_DIR_GLOBAL_RESET);
+      PerformReset (CBM_DIR_GLOBAL_RESET);
       break;
 
     case CBM_DIR_CONTINUE_POST:
@@ -333,7 +332,6 @@ PerformReset (
   UINT8       ResetType
   )
 {
-  EFI_STATUS  Status;
   UINT32      Data32;
   UINT32      GpioBase;
   UINT8       Reset;
@@ -342,7 +340,7 @@ PerformReset (
   Reset     = 0;
   GpioBase  = 0;
 
-  Status = ClearDISB ();
+  ClearDISB ();
 
   ETR = (UINT32) MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PMC, PCI_FUNCTION_NUMBER_PMC_IPC1, R_PMC_PMIR);
   MmioAnd32 (
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SmmHeci2PowerManagementLib/SmmHeci2PowerManagementLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SmmHeci2PowerManagementLib/SmmHeci2PowerManagementLib.c
index 4bf66dc78..79b5935e4 100644
--- a/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SmmHeci2PowerManagementLib/SmmHeci2PowerManagementLib.c
+++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Txe/Library/SmmHeci2PowerManagementLib/SmmHeci2PowerManagementLib.c
@@ -1,7 +1,7 @@
 /** @file
   Implementation file for the HECI2 Power Management library.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016-2017, Intel Corporation. All rights reserved.<BR>
 
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -41,7 +41,7 @@ GetHeci2PmProtocol (
     Status = gSmst->SmmLocateProtocol (
                       &gEfiHeci2PmProtocolGuid,
                       NULL,
-                      &mHeci2PmProtocol
+                      (VOID **)&mHeci2PmProtocol
                       );
 
     if (EFI_ERROR (Status)) {
-- 
2.11.0.windows.1



^ permalink raw reply related	[flat|nested] 3+ messages in thread