From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web10.1257.1580868772353384328 for ; Tue, 04 Feb 2020 18:12:53 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: zhichao.gao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Feb 2020 18:12:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,404,1574150400"; d="scan'208";a="224789060" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga007.fm.intel.com with ESMTP; 04 Feb 2020 18:12:51 -0800 Received: from shsmsx605.ccr.corp.intel.com (10.109.6.215) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 4 Feb 2020 18:12:51 -0800 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by SHSMSX605.ccr.corp.intel.com (10.109.6.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 5 Feb 2020 10:12:49 +0800 Received: from shsmsx603.ccr.corp.intel.com ([10.109.6.143]) by SHSMSX603.ccr.corp.intel.com ([10.109.6.143]) with mapi id 15.01.1713.004; Wed, 5 Feb 2020 10:12:49 +0800 From: "Gao, Zhichao" To: "devel@edk2.groups.io" , "ashishsingha@nvidia.com" , "Wang, Jian J" , "Wu, Hao A" , "Ni, Ray" Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready Thread-Topic: [edk2-devel] [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready Thread-Index: AQHV1TzVRksoQs7k2EWI0lfx0BtTP6gKhC8w Date: Wed, 5 Feb 2020 02:12:49 +0000 Message-ID: <7728b0a11fd84025a11a315b6a1977e3@intel.com> References: <5d9ffe00de052a95ac04319951d7466644cf78c1.1580147315.git.ashishsingha@nvidia.com> In-Reply-To: <5d9ffe00de052a95ac04319951d7466644cf78c1.1580147315.git.ashishsingha@nvidia.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjk0MmMyYTctNWY0Ni00OGNmLTgxYzctOWE5Mjk1YmQyNzVlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoid1NVUmptU1VYRzVkQWFRMmZmcGdhTWJ0RDFWVzRscWpxSnBFWHptSGFzYkI2VE04Tmlsc3JpOGY4U3QybDRZeCJ9 dlp-reaction: no-action dlp-version: 11.2.0.6 x-originating-ip: [10.239.127.36] MIME-Version: 1.0 Return-Path: zhichao.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Zhichao Gao Thanks, Zhichao > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Ashish > Singhal > Sent: Tuesday, January 28, 2020 1:53 AM > To: devel@edk2.groups.io; Wang, Jian J ; Wu, Hao = A > ; Gao, Zhichao ; Ni, Ray > > Cc: Ashish Singhal > Subject: [edk2-devel] [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix > Serial Port Ready >=20 > Before writing data to FIFO, wait for the serial port to be ready, to ma= ke sure > both the transmit FIFO and shift register empty. Code comment was saying= the > right thing but code was missing a check. >=20 > Signed-off-by: Ashish Singhal > --- > .../Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > index bbae379887..9cb50dd80d 100644 > --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550= .c > +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550 > +++ .c > @@ -646,7 +646,7 @@ SerialPortWrite ( > // Wait for the serial port to be ready, to make sure both the tran= smit FIFO > // and shift register empty. > // > - while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & > B_UART_LSR_TEMT) =3D=3D 0); > + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & > + (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) !=3D (B_UART_LSR_TEMT | > + B_UART_LSR_TXRDY)); >=20 > // > // Fill then entire Tx FIFO > -- > 2.17.1 >=20 >=20 >=20