From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: pbonzini@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 21 Aug 2019 23:18:35 -0700 Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A6EC18665D for ; Thu, 22 Aug 2019 06:18:34 +0000 (UTC) Received: by mail-wr1-f72.google.com with SMTP id m7so2676016wrw.22 for ; Wed, 21 Aug 2019 23:18:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=iiBEH8fXUbhWBIB4wbYVRRr/TM6QjP1OwASK7bN4h0Q=; b=YbP8hdSEsjHcYTlARF+JYwSL6DG3/nVLJa38wAccat1sBfPCUydRuU1MPBPakk0tf5 rFmMyCxXuOjnfDznAfIDrzvJv92cyuCLB44emgYzhTCLZR8DHWzVGpal2GJALObf3GS1 bn4nhoyKDL0rsJxAAMyMepcfZKvfcxs8awDYimrGxf9k5xaZac1oDJfv0qcpj++nBkzt QSpBAEXl64W1Cw6DR+vvAeC+NPN9Voh35ZPzo9hGp1lA9knsuYlnvMZkakUQ/ro7SZCj UuOXtj2GBMIavysDtCnGZXeupJY1/PDKmWdmYBzqQNhh5lg1zQ80175S3kEqIs1opIqc NcIw== X-Gm-Message-State: APjAAAU5pk3xC5Gx5Pa9rLj9AVRfog7Sx4mr7NiXRJAQC94MUPbNJHd5 W5tjZXYgXQjSo5Vrbd1bwtDXronvd4O8/WEe9arl7oGbeSCJT0qv5k1ICsJGwzTcq1JF82GC3AU wxh0N/bfDHdctJQ== X-Received: by 2002:adf:f851:: with SMTP id d17mr17409295wrq.77.1566454713267; Wed, 21 Aug 2019 23:18:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqzG1lOk+FLkDtdneMHPZRxRAGC20uZGPXtwxtDRUpjMAuYdrTgBUAcoPtH0Oq6hzwejRDZnwg== X-Received: by 2002:adf:f851:: with SMTP id d17mr17409267wrq.77.1566454712945; Wed, 21 Aug 2019 23:18:32 -0700 (PDT) Received: from ?IPv6:2001:b07:6468:f312:21b9:ff1f:a96c:9fb3? ([2001:b07:6468:f312:21b9:ff1f:a96c:9fb3]) by smtp.gmail.com with ESMTPSA id b3sm43343624wrm.72.2019.08.21.23.18.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Aug 2019 23:18:32 -0700 (PDT) Subject: Re: [edk2-rfc] [edk2-devel] CPU hotplug using SMM with QEMU+OVMF To: "Kinney, Michael D" , "rfc@edk2.groups.io" , "Yao, Jiewen" Cc: Alex Williamson , Laszlo Ersek , "devel@edk2.groups.io" , qemu devel list , Igor Mammedov , "Chen, Yingwen" , "Nakajima, Jun" , Boris Ostrovsky , Joao Marcal Lemos Martins , Phillip Goerl References: <8091f6e8-b1ec-f017-1430-00b0255729f4@redhat.com> <047801f8-624a-2300-3cf7-1daa1395ce59@redhat.com> <99219f81-33a3-f447-95f8-f10341d70084@redhat.com> <6f8b9507-58d0-5fbd-b827-c7194b3b2948@redhat.com> <74D8A39837DF1E4DA445A8C0B3885C503F75FAD3@shsmsx102.ccr.corp.intel.com> <7cb458ea-956e-c1df-33f7-025e4f0f22df@redhat.com> <74D8A39837DF1E4DA445A8C0B3885C503F7600B9@shsmsx102.ccr.corp.intel.com> <20190816161933.7d30a881@x1.home> <74D8A39837DF1E4DA445A8C0B3885C503F761B96@shsmsx102.ccr.corp.intel.com> <35396800-32d2-c25f-b0d0-2d7cd8438687@redhat.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: <772d64f7-e153-e9e6-dd69-9f34de5bb577@redhat.com> Date: Thu, 22 Aug 2019 08:18:30 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 21/08/19 22:17, Kinney, Michael D wrote: > Paolo, > > It makes sense to match real HW. Note that it'd also be fine to match some kind of official Intel specification even if no processor (currently?) supports it. > That puts us back to > the reset vector and handling the initial SMI at > 3000:8000. That is all workable from a FW implementation > perspective. It look like the only issue left is DMA. > > DMA protection of memory ranges is a chipset feature. > For the current QEMU implementation, what ranges of > memory are guaranteed to be protected from DMA? Is > it only A/B seg and TSEG? Yes. Paolo >> Yes, all of these would work. Again, I'm interested in >> having something that has a hope of being implemented in >> real hardware. >> >> Another, far easier to implement possibility could be a >> lockable MSR (could be the existing >> MSR_SMM_FEATURE_CONTROL) that allows programming the >> SMBASE outside SMM. It would be nice if such a bit >> could be defined by Intel. >> >> Paolo