From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id C2D217803DB for ; Wed, 22 Nov 2023 04:06:18 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=gp9b2KBc81xlh/60bvJff6F7qHpbTIaTWapaaFQcBUI=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1700625977; v=1; b=FHAYz/ryNUEt3Hwg9/KYm4NR1uuGhdpiSr6M22LdVoOsKWUNkUGXdeK5LzqdfXmAkTg4xa7f OuxeMI7KHCixJCXviZp3qamBz/poINbyM0FXklplALyzsfpR7K7KZNKlClXzKEMdwiaZW7rii4L jFv9LgIzSmm+XQWcfH5Z/5tg= X-Received: by 127.0.0.2 with SMTP id osY2YY7687511xk1KR3DLiBp; Tue, 21 Nov 2023 20:06:17 -0800 X-Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by mx.groups.io with SMTP id smtpd.web10.12300.1700625975769040941 for ; Tue, 21 Nov 2023 20:06:16 -0800 X-Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 84A6E24E238; Wed, 22 Nov 2023 12:06:13 +0800 (CST) X-Received: from EXMBX072.cuchost.com (172.16.6.82) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 22 Nov 2023 12:06:13 +0800 X-Received: from EXMBX073.cuchost.com (172.16.6.83) by EXMBX072.cuchost.com (172.16.6.82) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 22 Nov 2023 12:06:13 +0800 X-Received: from EXMBX073.cuchost.com ([fe80::f954:8a39:4422:a9cd]) by EXMBX073.cuchost.com ([fe80::f954:8a39:4422:a9cd%16]) with mapi id 15.00.1497.044; Wed, 22 Nov 2023 12:06:13 +0800 From: "John Chew" To: "devel@edk2.groups.io" , Leif Lindholm , Ard Biesheuvel CC: Sunil V L , Li Yong Subject: Re: [edk2-devel] [PATCH v3 0/5] Designware MMCDXE changes and enhancement Thread-Topic: [PATCH v3 0/5] Designware MMCDXE changes and enhancement Thread-Index: AQHaDgC/HB3jQs7WEEG1bSyzOtVUkLCF1j0A Date: Wed, 22 Nov 2023 04:06:12 +0000 Message-ID: <77558b3ec3b749f9b21868e8be6b3a08@EXMBX073.cuchost.com> References: <20231103025131.1643-1-yuinyee.chew@starfivetech.com> In-Reply-To: <20231103025131.1643-1-yuinyee.chew@starfivetech.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [202.188.176.82] x-yovoleruleagent: yovoleflag MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuinyee.chew@starfivetech.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: eqohzuVJBnPLCgB62FuIOxrBx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="FHAYz/ry"; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Leif, Ard, By any chance you have time to review this series of patches? Thank you. Regards, John -----Original Message----- From: YuinYee Chew =20 Sent: Friday, November 3, 2023 10:51 AM To: devel@edk2.groups.io Cc: YuinYee Chew ; Sunil V L ; Leif Lindholm ; Ard Biesheuvel ; Michael D Kinney ; Li = Yong Subject: [PATCH v3 0/5] Designware MMCDXE changes and enhancement v3: - CC Ard in this patch series [John Chew] v2: - Added maintainer to all patch in this series [Sunil] - Implement addition memory allocation strategy, where dma buffer is force to allocation below 4GB (Please refer to pathc 0005) [Sunil] v1: This patch series involves the following changes: 1. Remove DMA enable in CTRL register 2. Added DMA polling handling for RX/TX=20 3. Integrate SD MMC handling into the driver Cc: Sunil V L Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Michael D Kinney Cc: Li Yong John Chew (1): DesignWare/DwEmmcDxe: Force DMA buffer to allocate below 4GB mindachen1987 (4): DesignWare/DwEmmcDxe: Enabled Internal IDMAC interrupt RX/TX register DesignWare/DwEmmcDxe: Add CPU little endian option DesignWare/DwEmmcDxe: Remove ARM dependency library DesignWare/DwEmmcDxe: Add handling for SDMMC Silicon/Synopsys/DesignWare/DesignWare.dec = | 3 + Silicon/Synopsys/DesignWare/DesignWare.dsc = | 1 + Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmc.h = | 70 +++-- Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.c = | 315 +++++++++++++++----- Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/DwEmmcDxe.inf = | 3 +- Silicon/Synopsys/DesignWare/Drivers/DwEmmcDxe/{DwEmmcDxe.inf =3D> DwSdmmcD= xe.inf} | 11 +- 6 files changed, 283 insertions(+), 120 deletions(-) copy Silicon/Synopsy= s/DesignWare/Drivers/DwEmmcDxe/{DwEmmcDxe.inf =3D> DwSdmmcDxe.inf} (74%) -- 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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