From: "Ashish Singhal" <ashishsingha@nvidia.com>
To: <devel@edk2.groups.io>, <leif@nuviainc.com>, <ardb+tianocore@kernel.org>
Cc: Ashish Singhal <ashishsingha@nvidia.com>
Subject: [PATCH] ArmPkg/TimerDxe: Delay End Of Interrupt Signal
Date: Mon, 11 Oct 2021 13:20:50 -0600 [thread overview]
Message-ID: <775695ba8b279068d82f2fd50486370d7eeb03c2.1633979944.git.ashishsingha@nvidia.com> (raw)
Timer interrupts are level triggered. Hence, signal end of
interrupt only after current interrupt has been cleared
after setting updated compare value.
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
---
ArmPkg/Drivers/TimerDxe/TimerDxe.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
index 0370620fae..56c9c353b3 100644
--- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c
+++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
@@ -300,10 +300,6 @@ TimerInterruptHandler (
//
OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
- // Signal end of interrupt early to help avoid losing subsequent ticks
- // from long duration handlers
- gInterrupt->EndOfInterrupt (gInterrupt, Source);
-
// Check if the timer interrupt is active
if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
@@ -335,6 +331,10 @@ TimerInterruptHandler (
ArmInstructionSynchronizationBarrier ();
}
+ // Timer interrupts are level triggered. Hence, signal end of interrupt only after current
+ // interrupt has been cleared after setting updated compare value.
+ gInterrupt->EndOfInterrupt (gInterrupt, Source);
+
gBS->RestoreTPL (OriginalTPL);
}
--
2.17.1
reply other threads:[~2021-10-11 19:21 UTC|newest]
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