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kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.35 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.35; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.35) by DM6NAM11FT022.mail.protection.outlook.com (10.13.172.210) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4587.18 via Frontend Transport; Mon, 11 Oct 2021 19:20:57 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 11 Oct 2021 19:20:56 +0000 Received: from ashishsingha-lnx.nvidia.com (172.20.187.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 11 Oct 2021 19:20:55 +0000 From: "Ashish Singhal" To: , , CC: Ashish Singhal Subject: [PATCH] ArmPkg/TimerDxe: Delay End Of Interrupt Signal Date: Mon, 11 Oct 2021 13:20:50 -0600 Message-ID: <775695ba8b279068d82f2fd50486370d7eeb03c2.1633979944.git.ashishsingha@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public Return-Path: ashishsingha@nvidia.com MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dc1a7a39-f030-412b-e5ab-08d98cec40d9 X-MS-TrafficTypeDiagnostic: BL0PR12MB2386: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:962; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 19:20:57.6748 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc1a7a39-f030-412b-e5ab-08d98cec40d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2386 Content-Type: text/plain Timer interrupts are level triggered. Hence, signal end of interrupt only after current interrupt has been cleared after setting updated compare value. Signed-off-by: Ashish Singhal --- ArmPkg/Drivers/TimerDxe/TimerDxe.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c index 0370620fae..56c9c353b3 100644 --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -300,10 +300,6 @@ TimerInterruptHandler ( // OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); - // Signal end of interrupt early to help avoid losing subsequent ticks - // from long duration handlers - gInterrupt->EndOfInterrupt (gInterrupt, Source); - // Check if the timer interrupt is active if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) { @@ -335,6 +331,10 @@ TimerInterruptHandler ( ArmInstructionSynchronizationBarrier (); } + // Timer interrupts are level triggered. Hence, signal end of interrupt only after current + // interrupt has been cleared after setting updated compare value. + gInterrupt->EndOfInterrupt (gInterrupt, Source); + gBS->RestoreTPL (OriginalTPL); } -- 2.17.1