From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.7401.1639642245924576476 for ; Thu, 16 Dec 2021 00:10:46 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=msrOcq7g; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: ashraf.ali.s@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639642245; x=1671178245; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=AzBvz0nEuXADCvuCpFZrE/rLAyEuAxy7Ny1lj3ispGs=; b=msrOcq7gA9QUXsFSvn5KwX7ttWnuzOplNkmyz+0qPW6TGLw1NpJLL2BY VmXPT+TEYFZ6JOebD4u7dSLZNhPG+CrhyIVwnlkj27JmFjSUBQH1UIUNv NwIj0yVWrWS5QAMy+8sba9dXdyUcWiDdgxqKDEPXzFQEvrjWKQcCPnS32 9D6WcBtIW03t+VU/egvGd/tKxUe6k+IFxrx3hsaPcAlfdEuUliHs04cq8 taT8Scq+4OcbLpIL9nZJb/nXOGT8kefjfPREAVT5SY9dM8GB/2eAQNAb/ NZgz7/0+pZ0tR/1+Zf77MVYkjF3Qh/SRJgB2QvpGWFYrybFjA+EP6AzzA Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10199"; a="239243507" X-IronPort-AV: E=Sophos;i="5.88,210,1635231600"; d="scan'208";a="239243507" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2021 00:10:45 -0800 X-IronPort-AV: E=Sophos;i="5.88,210,1635231600"; d="scan'208";a="465946597" Received: from basfe004.gar.corp.intel.com ([10.66.129.57]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2021 00:10:38 -0800 From: "Ashraf Ali S" To: devel@edk2.groups.io Cc: Ashraf Ali S , Chasel Chiu , Nate DeSimone , Star Zeng , Kuo Ted , Duggapu Chinni B , Rangasai V Chaganty , Digant H Solanki , Sangeetha V , Ray Ni Subject: [PATCH v8] IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type Date: Thu, 16 Dec 2021 13:40:20 +0530 Message-Id: <7886ad065bf2cb1b513300da04db32a698d4b590.1639642126.git.ashraf.ali.s@intel.com> X-Mailer: git-send-email 2.30.2.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642 when the module is not building in IA32 mode which will lead to building error. when a module built-in X64 function pointer will be the size of 64bit width which cannot be fit in 32bit address which will lead to error. to overcome this issue introducing the 2 new PCD's for the 64bit modules can consume it. based on the which pcd platform set, use that. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Kuo Ted Cc: Duggapu Chinni B Cc: Rangasai V Chaganty Cc: Digant H Solanki Cc: Sangeetha V Cc: Ray Ni Signed-off-by: Ashraf Ali S --- .../FspmWrapperPeim/FspmWrapperPeim.c | 25 ++++++++++++++++--- .../FspmWrapperPeim/FspmWrapperPeim.inf | 3 ++- .../FspsWrapperPeim/FspsWrapperPeim.c | 25 ++++++++++++++++--- .../FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++- IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 2 ++ 5 files changed, 50 insertions(+), 8 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c index 287e7f9159..49fbb27eca 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c @@ -3,7 +3,7 @@ register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi notify to call FspSiliconInit API. - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -38,6 +38,25 @@ extern EFI_GUID gFspHobGuid; +/** + Get the FSP M UPD Data address + + @return FSP-M UPD Data Address +**/ + +UINTN +EFIAPI +GetFspmUpdDataAddress ( + VOID + ) +{ + if (PcdGet64 (PcdFspmUpdDataAddress64) != 0) { + return (UINTN) PcdGet64 (PcdFspmUpdDataAddress64); + } else { + return (UINTN) PcdGet32 (PcdFspmUpdDataAddress); + } +} + /** Call FspMemoryInit API. @@ -67,7 +86,7 @@ PeiFspMemoryInit ( return EFI_DEVICE_ERROR; } - if ((PcdGet32 (PcdFspmUpdDataAddress) == 0) && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) { + if ((GetFspmUpdDataAddress () == 0) && (FspmHeaderPtr->CfgRegionSize != 0) && (FspmHeaderPtr->CfgRegionOffset != 0)) { // // Copy default FSP-M UPD data from Flash // @@ -79,7 +98,7 @@ PeiFspMemoryInit ( // // External UPD is ready, get the buffer from PCD pointer. // - FspmUpdDataPtr = (FSPM_UPD_COMMON *)PcdGet32 (PcdFspmUpdDataAddress); + FspmUpdDataPtr = (FSPM_UPD_COMMON *) GetFspmUpdDataAddress(); ASSERT (FspmUpdDataPtr != NULL); } diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf index 00166e56a0..5d0e021401 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf @@ -6,7 +6,7 @@ # register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi # notify to call FspSiliconInit API. # -# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -60,6 +60,7 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64 ## CONSUMES [Sources] FspmWrapperPeim.c diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index f7459a90b5..ddee9cd029 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -3,7 +3,7 @@ register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi notify to call FspSiliconInit API. - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -181,6 +181,25 @@ FspSiliconInitDoneGetFspHobList ( } } +/** + Get the FSP S UPD Data address + + @return FSP-S UPD Data Address +**/ + +UINTN +EFIAPI +GetFspsUpdDataAddress ( + VOID + ) +{ + if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) { + return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64); + } else { + return (UINTN) PcdGet32 (PcdFspsUpdDataAddress); + } +} + /** This function is for FSP dispatch mode to perform post FSP-S process. @@ -283,7 +302,7 @@ PeiMemoryDiscoveredNotify ( return EFI_DEVICE_ERROR; } - if ((PcdGet32 (PcdFspsUpdDataAddress) == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) { + if ((GetFspsUpdDataAddress () == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) { // // Copy default FSP-S UPD data from Flash // @@ -292,7 +311,7 @@ PeiMemoryDiscoveredNotify ( SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset); CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize); } else { - FspsUpdDataPtr = (FSPS_UPD_COMMON *)PcdGet32 (PcdFspsUpdDataAddress); + FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress(); ASSERT (FspsUpdDataPtr != NULL); } diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf index aeeca58d6d..da0049a654 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf @@ -6,7 +6,7 @@ # register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi # notify to call FspSiliconInit API. # -# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -68,6 +68,7 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspMeasurementConfig ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64 ## CONSUMES [Guids] gFspHobGuid ## CONSUMES ## HOB diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec index b8dac1b574..a5a8b8a19e 100644 --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec @@ -121,3 +121,5 @@ # gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000|UINT32|0x50000000 gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x00000000|UINT32|0x50000001 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress64|0x00000000|UINT64|0x50000002 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress64|0x00000000|UINT64|0x50000003 -- 2.30.2.windows.1