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From: =?UTF-8?B?Q29ydmluIEvDtmhuZQ==?= To: devel@edk2.groups.io, kraxel@redhat.com Cc: Michael Roth , Oliver Steffen , Jiewen Yao , Tom Lendacky , Laszlo Ersek , Min Xu , Ard Biesheuvel , Erdem Aktas Date: Wed, 22 May 2024 10:59:44 +0200 In-Reply-To: <20240130130441.772484-2-kraxel@redhat.com> References: <20240130130441.772484-1-kraxel@redhat.com> <20240130130441.772484-2-kraxel@redhat.com> Autocrypt: addr=corvink@FreeBSD.org; prefer-encrypt=mutual; keydata=mQINBGNjZaIBEADDTrDNf+0pwiuRPBdClcnZW83dH1UhuOi0u+A1J2SatEBbNaFVtXXAa vewCTuyV/ZbNidjlhq3R/pWyiKjFKvs5dj7PMCw+3z2D5OWpMdHg7TrB+fbdFPOEsu0zQVKNaO+pS KCfN0Re0m7bL3wuvl7PXvBufRwA3Guo1P4j3TXWaEkuso7VupTvE25zVGg9ONHrGOjA9RUy+Yg4Se 3NLgtUdjBgA21SBQTDvRQV4fDmVenlwvWeE0Xm8FcDcpQb6sJTihaDku78mi3Ux1HCk7rTcepVEB0 xIB6qmFxv0sLlDmVv6Z6qg1y/Q5m23Pgz60o3TulMPV4F+3Itm8ifU+wgVSzBZbD29GYkd7LKqMkF bhvfSBk+5db3vbYY5OD//+LTM5AV7e2AhXuXMvG1UNBqXqSJTTSy6KZz+qmPQO0zos0dq46p8o82l KiBEGD2Hu0p+u0OyV+MmRYo1NIBFVbOPXp2MvUVl5II0UIJ3+N9gLBmfGA+HEpVO8PnvdoT/5NQ7m 8JK1rQHzjiDub/iDPAYMqKH4C0eZ/7zO0fuY5FeRNtuNtpH1Bw/+7/5RJH7bcKkfGHHEp15FJUrGH gWNydoDLB9QBprwQc8FEldDXBjzOMXIgh6FGKLNu6DswvIPGy6M3u7DXwDakCXz+c9Ym0oFihLzZx WntrsxdswD/CwARAQABtCdDb3J2aW4gS8O2aG5lIDxjb3J2aW4ua29laG5lQGdtYWlsLmNvbT6JAl QEEwEIAD4WIQSC9FKVreba38fZT0bYVNpWMV4CagUCZArUIwIbAwUJCWYBgAULCQgHAgYVCgkICwI EFgIDAQIeAQIXgAAKCRDYVNpWMV4CalcID/44k2i/mqSSi4W6FAobSF1nFLtP/pfcRNJriWKx2UF7 cfFMKyg7Nilg7FhLb5FDB1umUW2nFfchFPTUp4FfKzgRvPzIMg4RIRcVtTpYbl3z7zs9ZXD8qS//i ibbiUG3quncm6tO2x1jLZD3ORC+8MuLGXhYQIa4O5vVF2SBHdb/U6P+wsrF+U+OpRdEdQ/4Xu9S02 kltzBGgArjcexdhUqEqW01KCCSH0+qgfN1NE+9L934ZOB+cai2b9apPbCOGuV6KcUKMj4z0RWInhl XIyMqtmhdix/P/GjrQ1REVNdp74JeweSSedM15wwc6YLMXPrtOnnExyZ1gyNFYaub+Mdo3ZQ+8386 3B0C9IlpzEW0K8bYlZrl4WBNdcMOyByETAxgQmBgP6ZFErTtaeUOH1nX2FyR6o2GLSahRgngQmnRE zScTpPbBEkMwJMDAO+rbjjGxjeKSUwD1WOfbI6QZj+MS/uBk2p08kgN7fQaCEwj6jqML/IIE+FZ9I In6TNG0hChD384VHO+YioLBno1Atgi4Q7JUWSRIHQXZW+StQajFrWPPyKQwCe1MwqpKoMpX/q8IZB lzwJgZS8ShLeFZjtzOt1jgM99TD91Neonf9OzjTSbfo7sJviSWoICMhB/MvDZjj+naMVF86uGFxnI EsjVKyBxlJd4TRHnLYPTIHFKBLQjQ29ydmluIEvDtmhuZSA8Y29ydmlua0BGcmVlQlNELm9yZz6JA lQEEwEKAD4WIQSC9FKVreba38fZT0bYVNpWMV4CagUCY2NlogIbAwUJCWYBgAULCQgHAwUVCgkICw UWAwIBAAIeAQIXgAAKCRDYVNpWMV4CavfDEACCFnXpR7H9eOgP+GJMNPtK6i9/xnqdyXi8uCZIN0h YwjN4Xzo9SMLOf4UUlQEveOB+bGqbRfHd/fGKnrlXiPd0SGpKWJC21gqL/DsIH0J8I3Whth+O8tfP WeFy0oCsvBaaGFLIrDfoIgHF9i/gqEe48xhN42weB02Z3mdR1L0d7ME/BLwS0mCXe9Zh3uHw63S6x YB3Wsjptxe/ph6TpQDUKWtRJkjC6BqXPBdThpbbfIRWmjZbp2fKEJPvtRXS14+gbUqWeJ4xCvprA3 +ae7vtrp91X775yngyW3XTw5cmDiJIjykH8+zhEIoNQXNBpFrehkQDYrcM+WoE6NGSJo+3VJvSRWh UGWDVrxdTYNkbIjmTNlkI12NINC007DiuV7OF9XHWgrbbylvuZvbODmbJRdhTFy9upAUygX1/xUAQ EIMqMiJmyTdv8i0IbZ611WElQx9XHgGeZgM6+39/laN8FwspM6gE/4NzZHIZN0LEBOerZqoF+Il6e ccQpoEWx7nb/RilJp3dUUyvkBnJWg+AJByosg857kvvmDnZ3UB+bejWpcfFvnbkiKPUBPDO7tWPb5 r2yFDpDe/Vg5x+sRbkkXGUFD6Rx0p/ZiRIneVVg8emTzhDR0IL/BZkq/uVJkdaphZli1F/31cNgf6 ZJYnjxlk86uiYSySZQR0dKLDqq7QlQ29ydmluIEvDtmhuZSA8Yy5rb2VobmVAYmVja2hvZmYuY29t PokCVAQTAQgAPhYhBIL0UpWt5trfx9lPRthU2lYxXgJqBQJkCtScAhsDBQkJZgGABQsJCAcCBhUKC QgLAgQWAgMBAh4BAheAAAoJENhU2lYxXgJqI+QQAML5PTR7KpUFV3SLG60LQJGEOHUfDmJYczxBFb IAq1U4hIbivopu1AdLty7oDDrIjCVoa2/Cy34dd99O7lhLvUmZFB/zDSUtbUg2zhDkU0YSZ11Fdrl Wzky2tFaQRgxpDvWlUP0baa3Pd4dPDRiIUI6AOSR2SL6XANk6sJh56gLVM6G8yyafGsxSyDYg6Z78 EEMFejHwB+KP2DdsahupzM+F97HeC1+bOHYxtqN+2hEkPLtQWizyumPqNg5FvZhwe7yO8V95hF3Rh uDO+9aJT+WLLvcZEb/L1bI04IvZ5FWgCLI7Levd/DuOtZI8gWapHhqGZRbXB2fuJkCoKCl6V67h/7 aWhU3LjFTsC5siJyrxPjapKcIk8a7PqZDswNCKR+24LJ5D59mPgEOnsiCCVpik1WE/kgD+rOu9dQx jpjKwuKowf4EJP1KYNkYtoy1HthzyTOqPwqXC3IUl0GVPO3xw6MhUM3irCVFruC+ecVrv85Rd37vr duT6JvgW92xjWegMsamtkDZH8Ik/cmYhH0K/qEc6OZVNea/4PTEZe0uxODJ6pbMd80AJyGqDPPVeA gWJtEIG4k6IS8XyD5v1QJtlpDVpPwP/bbFnVc3h3Oatfn8Etm1KAqYvNwyO+om2PkF1p732uapDZd LwksVmgc9s79+9pSpeP5DbIeMzhrIK User-Agent: Evolution 3.52.1 MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 22 May 2024 01:59:49 -0700 Resent-From: corvink@FreeBSD.org Reply-To: devel@edk2.groups.io,corvink@FreeBSD.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: KRr5botadURzyYm4qEMHDlkEx7686176AA= Content-Type: multipart/signed; micalg="pgp-sha256"; protocol="application/pgp-signature"; boundary="=-m9pNaYfz0XSWlX5rz7qO" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=bMuQldcS; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=FreeBSD.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io --=-m9pNaYfz0XSWlX5rz7qO Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2024-01-30 at 14:04 +0100, Gerd Hoffmann wrote: > Specifically before running lzma uncompress of the main firmware > volume. > This is needed to make sure caching is enabled, otherwise the > uncompress > can be extremely slow. >=20 > Adapt the ASSERTs and MTRR setup in PlatformInitLib to the changes. >=20 > Background:=C2=A0 Depending on virtual machine configuration kvm may uses > EPT > memory types to apply guest MTRR settings.=C2=A0 In case MTRRs are > disabled > kvm will use the uncachable memory type for all mappings.=C2=A0 The > vmx_get_mt_mask() function in the linux kernel handles this and can > be > found here: >=20 > https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arc= h/x86/kvm/vmx/vmx.c?h=3Dv6.7.1#n7580 >=20 > In most VM configurations kvm uses MTRR_TYPE_WRBACK unconditionally.=C2= =A0 > In > case the VM has a mdev device assigned that is not the case though. >=20 > Before commit e8aa4c6546ad ("UefiCpuPkg/ResetVector: Cache Disable > should not be set by default in CR0") kvm also ended up using > MTRR_TYPE_WRBACK due to KVM_X86_QUIRK_CD_NW_CLEARED.=C2=A0 After that > commit > kvm evaluates guest mtrr settings, which why setting up MTRRs early > is > important now. >=20 > Signed-off-by: Gerd Hoffmann > --- > =C2=A0OvmfPkg/IntelTdx/Sec/SecMain.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 32 > +++++++++++++++++++++ > =C2=A0OvmfPkg/Library/PlatformInitLib/MemDetect.c | 10 +++---- > =C2=A0OvmfPkg/Sec/SecMain.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 | 32 > +++++++++++++++++++++ > =C2=A03 files changed, 69 insertions(+), 5 deletions(-) >=20 > diff --git a/OvmfPkg/IntelTdx/Sec/SecMain.c > b/OvmfPkg/IntelTdx/Sec/SecMain.c > index 42a587adfa57..a218ca17a01a 100644 > --- a/OvmfPkg/IntelTdx/Sec/SecMain.c > +++ b/OvmfPkg/IntelTdx/Sec/SecMain.c > @@ -27,6 +27,8 @@ > =C2=A0#include > =C2=A0#include > =C2=A0#include > +#include > +#include > =C2=A0 > =C2=A0#define SEC_IDT_ENTRY_COUNT=C2=A0 34 > =C2=A0 > @@ -48,6 +50,31 @@ IA32_IDT_GATE_DESCRIPTOR=C2=A0 mIdtEntryTemplate =3D { > =C2=A0=C2=A0 } > =C2=A0}; > =C2=A0 > +// > +// Enable MTRR early, set default type to write back. > +// Needed to make sure caching is enabled, > +// without this lzma decompress can be very slow. > +// > +STATIC > +VOID > +SecMtrrSetup ( > +=C2=A0 VOID > +=C2=A0 ) > +{ > +=C2=A0 CPUID_VERSION_INFO_EDX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 Edx; > +=C2=A0 MSR_IA32_MTRR_DEF_TYPE_REGISTER=C2=A0 DefType; > + > +=C2=A0 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32); > +=C2=A0 if (!Edx.Bits.MTRR) { > +=C2=A0=C2=A0=C2=A0 return; > +=C2=A0 } > + > +=C2=A0 DefType.Uint64=C2=A0=C2=A0=C2=A0 =3D AsmReadMsr64 (MSR_IA32_MTRR_= DEF_TYPE); > +=C2=A0 DefType.Bits.Type =3D 6; /* write back */ > +=C2=A0 DefType.Bits.E=C2=A0=C2=A0=C2=A0 =3D 1; /* enable */ > +=C2=A0 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64); > +} > + > =C2=A0VOID > =C2=A0EFIAPI > =C2=A0SecCoreStartupWithStack ( > @@ -204,6 +231,11 @@ SecCoreStartupWithStack ( > =C2=A0=C2=A0 InitializeApicTimer (0, MAX_UINT32, TRUE, 5); > =C2=A0=C2=A0 DisableApicTimerInterrupt (); > =C2=A0 > +=C2=A0 // > +=C2=A0 // Initialize MTRR > +=C2=A0 // > +=C2=A0 SecMtrrSetup (); > + > =C2=A0=C2=A0 PeilessStartup (&SecCoreData); > =C2=A0 > =C2=A0=C2=A0 ASSERT (FALSE); > diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c > b/OvmfPkg/Library/PlatformInitLib/MemDetect.c > index f042517bb64a..e89f63eee054 100644 > --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c > +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c > @@ -1082,18 +1082,18 @@ PlatformQemuInitializeRam ( > =C2=A0=C2=A0=C2=A0=C2=A0 MtrrGetAllMtrrs (&MtrrSettings); > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0 // > -=C2=A0=C2=A0=C2=A0 // MTRRs disabled, fixed MTRRs disabled, default type= is > uncached > +=C2=A0=C2=A0=C2=A0 // See SecMtrrSetup(), default type should be write b= ack > =C2=A0=C2=A0=C2=A0=C2=A0 // > -=C2=A0=C2=A0=C2=A0 ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); > +=C2=A0=C2=A0=C2=A0 ASSERT ((MtrrSettings.MtrrDefType & BIT11) !=3D 0); > =C2=A0=C2=A0=C2=A0=C2=A0 ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D= =3D 0); > -=C2=A0=C2=A0=C2=A0 ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); > +=C2=A0=C2=A0=C2=A0 ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D > MTRR_CACHE_WRITE_BACK); > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0 // > =C2=A0=C2=A0=C2=A0=C2=A0 // flip default type to writeback > =C2=A0=C2=A0=C2=A0=C2=A0 // > -=C2=A0=C2=A0=C2=A0 SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixe= d, 0x06); > +=C2=A0=C2=A0=C2=A0 SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixe= d, > MTRR_CACHE_WRITE_BACK); > =C2=A0=C2=A0=C2=A0=C2=A0 ZeroMem (&MtrrSettings.Variables, sizeof > MtrrSettings.Variables); > -=C2=A0=C2=A0=C2=A0 MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; > +=C2=A0=C2=A0=C2=A0 MtrrSettings.MtrrDefType |=3D BIT10; > =C2=A0=C2=A0=C2=A0=C2=A0 MtrrSetAllMtrrs (&MtrrSettings); > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0 // This has to be changed for OvmfPkg/Bhyve/PlatformPei/MemDetect.c too. > diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c > index 31da5d0ace51..46c54f2984ff 100644 > --- a/OvmfPkg/Sec/SecMain.c > +++ b/OvmfPkg/Sec/SecMain.c > @@ -30,6 +30,8 @@ > =C2=A0#include > =C2=A0#include > =C2=A0#include > +#include > +#include > =C2=A0#include "AmdSev.h" > =C2=A0 > =C2=A0#define SEC_IDT_ENTRY_COUNT=C2=A0 34 > @@ -744,6 +746,31 @@ FindAndReportEntryPoints ( > =C2=A0=C2=A0 return; > =C2=A0} > =C2=A0 > +// > +// Enable MTRR early, set default type to write back. > +// Needed to make sure caching is enabled, > +// without this lzma decompress can be very slow. > +// > +STATIC > +VOID > +SecMtrrSetup ( > +=C2=A0 VOID > +=C2=A0 ) > +{ > +=C2=A0 CPUID_VERSION_INFO_EDX=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 Edx; > +=C2=A0 MSR_IA32_MTRR_DEF_TYPE_REGISTER=C2=A0 DefType; > + > +=C2=A0 AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &Edx.Uint32); > +=C2=A0 if (!Edx.Bits.MTRR) { > +=C2=A0=C2=A0=C2=A0 return; > +=C2=A0 } > + > +=C2=A0 DefType.Uint64=C2=A0=C2=A0=C2=A0 =3D AsmReadMsr64 (MSR_IA32_MTRR_= DEF_TYPE); > +=C2=A0 DefType.Bits.Type =3D 6; /* write back */ > +=C2=A0 DefType.Bits.E=C2=A0=C2=A0=C2=A0 =3D 1; /* enable */ > +=C2=A0 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64); > +} > + > =C2=A0VOID > =C2=A0EFIAPI > =C2=A0SecCoreStartupWithStack ( > @@ -942,6 +969,11 @@ SecCoreStartupWithStack ( > =C2=A0=C2=A0 InitializeApicTimer (0, MAX_UINT32, TRUE, 5); > =C2=A0=C2=A0 DisableApicTimerInterrupt (); > =C2=A0 > +=C2=A0 // > +=C2=A0 // Initialize MTRR > +=C2=A0 // > +=C2=A0 SecMtrrSetup (); > + > =C2=A0=C2=A0 // > =C2=A0=C2=A0 // Initialize Debug Agent to support source level debug in S= EC/PEI > phases before memory ready. > =C2=A0=C2=A0 // --=20 Kind regards, Corvin -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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