From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id E27B0D80696 for ; Mon, 30 Oct 2023 09:40:29 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=LTemWV4enKBS6YCtYEzDA1fN6820JX6itW2grZORyrE=; c=relaxed/simple; d=groups.io; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1698658828; v=1; b=Y+0DwJEqsAhoHreq6iMnhNZg2JAMu19GOJ3thiLKBm4T+wW/t0t3A3DfdtI1PD+Ja+APg/Cv 6hd2Zi0+Ju9dUSxkMd2SEinQoYN9sjCMVS586jKSZlGW8StgjGUXp5rxQlX1MDumKdx00BAf1Gg JuIeFsBquWcIYjMuinyjlfA8= X-Received: by 127.0.0.2 with SMTP id AYowYY7687511xz0sWSAtDf4; Mon, 30 Oct 2023 02:40:28 -0700 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web10.144821.1698658827931591683 for ; Mon, 30 Oct 2023 02:40:28 -0700 X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-552-WffLMkQEP82R49DQowyjYw-1; Mon, 30 Oct 2023 05:40:22 -0400 X-MC-Unique: WffLMkQEP82R49DQowyjYw-1 X-Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 147AC8007B3; Mon, 30 Oct 2023 09:40:22 +0000 (UTC) X-Received: from [10.39.194.199] (unknown [10.39.194.199]) by smtp.corp.redhat.com (Postfix) with ESMTPS id ADF0F1C060B1; Mon, 30 Oct 2023 09:40:20 +0000 (UTC) Message-ID: <79310567-90e5-4426-9cf4-41d25348aaef@redhat.com> Date: Mon, 30 Oct 2023 10:40:19 +0100 MIME-Version: 1.0 Subject: Re: [edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V To: Pedro Falcato , devel@edk2.groups.io, dhaval@rivosinc.com Cc: Michael D Kinney , Liming Gao , Zhiguang Liu References: <20231029144613.150580-1-dhaval@rivosinc.com> <20231029144613.150580-5-dhaval@rivosinc.com> From: "Laszlo Ersek" In-Reply-To: X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: snP3vv4pzWha1WZIjo6L7EAax7686176AA= Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Y+0DwJEq; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=redhat.com (policy=none) On 10/29/23 20:07, Pedro Falcato wrote: > On Sun, Oct 29, 2023 at 2:46 PM Dhaval Sharma wrote: >> >> Use newly defined cache management operations for RISC-V where possible >> It builds up on the support added for RISC-V cache management >> instructions in BaseLib. >> Cc: Michael D Kinney >> Cc: Liming Gao >> Cc: Zhiguang Liu >> Cc: Laszlo Ersek >> >> Signed-off-by: Dhaval Sharma >> Acked-by: Laszlo Ersek >> --- >> >> Notes: >> V7: >> - Added PcdLib >> - Restructure DEBUG message based on feedback on V6 >> - Make naming consistent to CMO, remove all CBO references >> - Add ASSERT for not supported functions instead of plain debug message >> - Added RB tag >> V6: >> - Utilize cache management instructions if HW supports it >> This patch is part of restructuring on top of v5 >> >> MdePkg/MdePkg.dec | 8 + >> MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 5 + >> MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 168 +++++++++++++++++--- >> MdePkg/MdePkg.uni | 4 + >> 4 files changed, 165 insertions(+), 20 deletions(-) >> >> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec >> index ac54338089e8..fa92673ff633 100644 >> --- a/MdePkg/MdePkg.dec >> +++ b/MdePkg/MdePkg.dec >> @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64] >> # @Prompt CPU Rng algorithm's GUID. >> gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037 >> >> +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] >> + # >> + # Configurability to override RISC-V CPU Features >> + # BIT 0 = Cache Management Operations. This bit is relevant only if >> + # previous stage has feature enabled and user wants to disable it. >> + # >> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69 >> + >> [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] >> ## This value is used to set the base address of PCI express hierarchy. >> # @Prompt PCI Express Base Address. >> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf >> index 6fd9cbe5f6c9..601a38d6c109 100644 >> --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf >> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf >> @@ -56,3 +56,8 @@ [LibraryClasses] >> BaseLib >> DebugLib >> >> +[LibraryClasses.RISCV64] >> + PcdLib >> + >> +[Pcd.RISCV64] >> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES >> diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c >> index 4eb18edb9aa7..5b3104afb67e 100644 >> --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c >> +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c >> @@ -2,6 +2,7 @@ >> RISC-V specific functionality for cache. >> >> Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
>> + Copyright (c) 2023, Rivos Inc. All rights reserved.
>> >> SPDX-License-Identifier: BSD-2-Clause-Patent >> **/ >> @@ -9,10 +10,115 @@ >> #include >> #include >> #include >> +#include >> + >> +// >> +// TODO: Grab cache block size and make Cache Management Operation >> +// enabling decision based on RISC-V CPU HOB in >> +// future when it is available. >> +// >> +#define RISCV_CACHE_BLOCK_SIZE 64 >> +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1 >> + >> +typedef enum { >> + Clean, >> + Flush, >> + Invld, >> +} CACHE_OP; > > small nit: You may want to do something like CACHE_OP_{CLEAN, FLUSH, > INVID}. but since this is a file-local enum I don't consider this > merge-blocking. > Agree with you on the prefix, but not on the uppercase spelling; edk2 (and UEFI) uses CamelCase enumeration constants. Compare: at the very top of "MdePkg/Include/Uefi/UefiSpec.h", we have EFI_ALLOCATE_TYPE with constants like AllocateAnyPages. Laszlo -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110304): https://edk2.groups.io/g/devel/message/110304 Mute This Topic: https://groups.io/mt/102256468/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/1913456212/xyzzy [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-