From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3D8CE2116822C for ; Fri, 19 Oct 2018 06:32:41 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 84FA23078AAF; Fri, 19 Oct 2018 13:32:40 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-18.rdu2.redhat.com [10.10.121.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7576C5DD6B; Fri, 19 Oct 2018 13:32:39 +0000 (UTC) To: Eric Dong , edk2-devel@lists.01.org Cc: Ruiyu Ni References: <20181019020622.6864-1-eric.dong@intel.com> <20181019020622.6864-2-eric.dong@intel.com> From: Laszlo Ersek Message-ID: <79584d9c-cd84-18bd-ec03-9f9afe3e01cc@redhat.com> Date: Fri, 19 Oct 2018 15:32:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181019020622.6864-2-eric.dong@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Fri, 19 Oct 2018 13:32:40 +0000 (UTC) Subject: Re: [Patch v4 1/6] UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Oct 2018 13:32:41 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 10/19/18 04:06, Eric Dong wrote: > v3 changes: > 1. Move CPU_FEATURE_DEPENDENCE_TYPE definition here from RegisterCpuFeaturesLib.h file. > 2. Add Invalid type for REGISTER_TYPE which will be used in code. > > v2 changes: > 1. Add more description about why we do this change. > 2. Change structure field type from pointer to EFI_PHYSICAL_ADDRESS because it will > be share between PEI and DXE. > > v1 Changes: > In order to support semaphore related logic, add new definition for it. > > In a system which has multiple cores, current set register value task costs huge times. > After investigation, current set MSR task costs most of the times. Current logic uses > SpinLock to let set MSR task as an single thread task for all cores. Because MSR has > scope attribute which may cause GP fault if multiple APs set MSR at the same time, > current logic use an easiest solution (use SpinLock) to avoid this issue, but it will > cost huge times. > > In order to fix this performance issue, new solution will set MSRs base on their scope > attribute. After this, the SpinLock will not needed. Without SpinLock, new issue raised > which is caused by MSR dependence. For example, MSR A depends on MSR B which means MSR A > must been set after MSR B has been set. Also MSR B is package scope level and MSR A is > thread scope level. If system has multiple threads, Thread 1 needs to set the thread level > MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for thread 1 > and thread 2 like below: > > Thread 1 Thread 2 > MSR B N Y > MSR A Y Y > > If driver don't control execute MSR order, for thread 1, it will execute MSR A first, but > at this time, MSR B not been executed yet by thread 2. system may trig exception at this > time. > > In order to fix the above issue, driver introduces semaphore logic to control the MSR > execute sequence. For the above case, a semaphore will be add between MSR A and B for > all threads. Semaphore has scope info for it. The possible scope value is core or package. > For each thread, when it meets a semaphore during it set registers, it will 1) release > semaphore (+1) for each threads in this core or package(based on the scope info for this > semaphore) 2) acquire semaphore (-1) for all the threads in this core or package(based > on the scope info for this semaphore). With these two steps, driver can control MSR > sequence. Sample code logic like below: > > // > // First increase semaphore count by 1 for processors in this package. > // > for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) { > LibReleaseSemaphore ((UINT32 *) &SemaphorePtr[PackageOffset + ProcessorIndex]); > } > // > // Second, check whether the count has reach the check number. > // > for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) { > LibWaitForSemaphore (&SemaphorePtr[ApOffset]); > } > > Platform Requirement: > 1. This change requires register MSR setting base on MSR scope info. If still register MSR > for all threads, exception may raised. > > Known limitation: > 1. Current CpuFeatures driver supports DXE instance and PEI instance. But semaphore logic > requires Aps execute in async mode which is not supported by PEI driver. So CpuFeature > PEI instance not works after this change. We plan to support async mode for PEI in phase > 2 for this task. > > Cc: Ruiyu Ni > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eric Dong > Reviewed-by: Ruiyu Ni > Reviewed-by: Laszlo Ersek > --- > UefiCpuPkg/Include/AcpiCpuData.h | 67 +++++++++++++++++++++++++++++++++++++++- > 1 file changed, 66 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h > index 9e51145c08..005d48d7ca 100644 > --- a/UefiCpuPkg/Include/AcpiCpuData.h > +++ b/UefiCpuPkg/Include/AcpiCpuData.h > @@ -22,9 +22,60 @@ typedef enum { > Msr, > ControlRegister, > MemoryMapped, > - CacheControl > + CacheControl, > + > + // > + // Semaphore type used to control the execute sequence of the Msr. > + // It will be insert between two Msr which has execute dependence. > + // > + Semaphore, > + InvalidReg > } REGISTER_TYPE; > > +// > +// Describe the dependency type for different features. > +// The value set to CPU_REGISTER_TABLE_ENTRY.Value when the REGISTER_TYPE is Semaphore. > +// > +typedef enum { > + NoneDepType, > + ThreadDepType, > + CoreDepType, > + PackageDepType, > + InvalidDepType > +} CPU_FEATURE_DEPENDENCE_TYPE; > + > +// > +// CPU information. > +// > +typedef struct { > + // > + // Record the package count in this CPU. > + // > + UINT32 PackageCount; > + // > + // Record the max core count in this CPU. > + // Different packages may have different core count, this value > + // save the max core count in all the packages. > + // > + UINT32 MaxCoreCount; > + // > + // Record the max thread count in this CPU. > + // Different cores may have different thread count, this value > + // save the max thread count in all the cores. > + // > + UINT32 MaxThreadCount; > + // > + // This field points to an array. > + // This array saves valid core count (type UINT32) of each package. > + // The array has PackageCount elements. > + // > + // If the platform does not support MSR setting at S3 resume, and > + // therefore it doesn't need the dependency semaphores, it should set > + // this field to 0. > + // > + EFI_PHYSICAL_ADDRESS ValidCoreCountPerPackage; > +} CPU_STATUS_INFORMATION; > + > // > // Element of register table entry > // > @@ -147,6 +198,20 @@ typedef struct { > // provided. > // > UINT32 ApMachineCheckHandlerSize; > + // > + // CPU information which is required when set the register table. > + // > + CPU_STATUS_INFORMATION CpuStatus; > + // > + // Location info for each AP. > + // It points to an array which saves all APs location info. > + // The array count is the AP count in this CPU. > + // > + // If the platform does not support MSR setting at S3 resume, and > + // therefore it doesn't need the dependency semaphores, it should set > + // this field to 0. > + // > + EFI_PHYSICAL_ADDRESS ApLocation; > } ACPI_CPU_DATA; > > #endif > Looks good, thank you! My R-b stands. Laszlo