From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rn-mailsvcp-ppex-lapp15.apple.com (rn-mailsvcp-ppex-lapp15.apple.com [17.179.253.34]) by mx.groups.io with SMTP id smtpd.web12.4591.1619567154582690542 for ; Tue, 27 Apr 2021 16:45:54 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@apple.com header.s=20180706 header.b=n1c9oJel; spf=pass (domain: apple.com, ip: 17.179.253.34, mailfrom: afish@apple.com) Received: from pps.filterd (rn-mailsvcp-ppex-lapp15.rno.apple.com [127.0.0.1]) by rn-mailsvcp-ppex-lapp15.rno.apple.com (8.16.1.2/8.16.1.2) with SMTP id 13RNgXpD027278; Tue, 27 Apr 2021 16:45:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apple.com; h=content-type : mime-version : subject : from : in-reply-to : date : cc : content-transfer-encoding : message-id : references : to; s=20180706; bh=F6erF4qDc7OCjnv1lb+LbcpQgqbRufQauMuPi95/R8w=; b=n1c9oJeli1S7Yq0xJR3POzeVTOhAIUy4qBfhmbX17B87lrmoQnEu0TdTz8k+WxKFoasw wArRUFa4kryVRY+CaQySPuOL3mQivNK8Wn6/5a0SP8cqJmeMaFxTTqGwfGRI/sSDh7ik Wa/B6HXpUDIODJ4to9pWVpQBuaFxjCG9uhgrirtOA01JWc7ce3OftVNZDLOCNG2ga04n Vbo0heBRKLOweLEmFqWEN/dZjw87rOuVBNK/qoCI2CkOEENH4c0mWJBNvb2E5KE4+Jl6 Vw9R0ijQXBUZb9QisVMOcEIB9/vThAob2KsknVLZZ9pckSJ7/N8z7raDHCw3xfINTkUK NA== Received: from rn-mailsvcp-mta-lapp04.rno.apple.com (rn-mailsvcp-mta-lapp04.rno.apple.com [10.225.203.152]) by rn-mailsvcp-ppex-lapp15.rno.apple.com with ESMTP id 384gwax4vx-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 27 Apr 2021 16:45:54 -0700 Received: from rn-mailsvcp-mmp-lapp02.rno.apple.com (rn-mailsvcp-mmp-lapp02.rno.apple.com [17.179.253.15]) by rn-mailsvcp-mta-lapp04.rno.apple.com (Oracle Communications Messaging Server 8.1.0.7.20201203 64bit (built Dec 3 2020)) with ESMTPS id <0QS800ULFY0HRR60@rn-mailsvcp-mta-lapp04.rno.apple.com>; Tue, 27 Apr 2021 16:45:53 -0700 (PDT) Received: from process_milters-daemon.rn-mailsvcp-mmp-lapp02.rno.apple.com by rn-mailsvcp-mmp-lapp02.rno.apple.com (Oracle Communications Messaging Server 8.1.0.7.20201203 64bit (built Dec 3 2020)) id <0QS800000XH9LG00@rn-mailsvcp-mmp-lapp02.rno.apple.com>; Tue, 27 Apr 2021 16:45:53 -0700 (PDT) X-Va-A: X-Va-T-CD: 6c7192f7554cb912fd7c9cbc31560ee2 X-Va-E-CD: f4dd3ccc251b56941c826d2c70ead673 X-Va-R-CD: 6353a72eb7abb219a4e9576c7769c664 X-Va-CD: 0 X-Va-ID: d973307f-67bc-4f7c-991b-fd01da689f43 X-V-A: X-V-T-CD: 6c7192f7554cb912fd7c9cbc31560ee2 X-V-E-CD: f4dd3ccc251b56941c826d2c70ead673 X-V-R-CD: 6353a72eb7abb219a4e9576c7769c664 X-V-CD: 0 X-V-ID: c566240a-71b2-49a4-8728-e9696e5ad51d X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-27_13:2021-04-27,2021-04-27 signatures=0 Received: from [17.235.56.131] (unknown [17.235.56.131]) by rn-mailsvcp-mmp-lapp02.rno.apple.com (Oracle Communications Messaging Server 8.1.0.7.20201203 64bit (built Dec 3 2020)) with ESMTPSA id <0QS800DEHY0GH000@rn-mailsvcp-mmp-lapp02.rno.apple.com>; Tue, 27 Apr 2021 16:45:53 -0700 (PDT) MIME-version: 1.0 (Mac OS X Mail 14.0 \(3654.20.0.2.1\)) Subject: Re: [edk2-devel] [PATCH V5 1/1] EmbeddedPkg: DwMmcHcDxe: Add support for Designware SDMMC driver From: "Andrew Fish" In-reply-to: <61871098-5a01-8125-ae9b-7ccac33d3577@ipxe.org> Date: Tue, 27 Apr 2021 16:45:52 -0700 Cc: edk2-devel-groups-io , tien.hock.loh@intel.com, Mike Kinney , "thloh85@gmail.com" , Leif Lindholm , Ard Biesheuvel Message-id: <7A9BDBC1-4107-41A3-9FE0-FAF502E390EC@apple.com> References: <20210322032439.9312-1-tien.hock.loh@intel.com> <20210322032439.9312-2-tien.hock.loh@intel.com> <09F9E77A-9B6B-4D5F-A7FF-F49EAFA03FEB@apple.com> <61871098-5a01-8125-ae9b-7ccac33d3577@ipxe.org> To: Michael Brown X-Mailer: Apple Mail (2.3654.20.0.2.1) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-27_13:2021-04-27,2021-04-27 signatures=0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: quoted-printable > On Apr 27, 2021, at 2:40 PM, Michael Brown wrote: >=20 > On 27/04/2021 18:31, Andrew Fish via groups.io wrote: >> One trick people have pulled in the past is to write a driver that = produces a =E2=80=9Cfake=E2=80=9D PCI IO Protocol. The =E2=80=9Cfake=E2=80= =9D PCI IO driver abstracts how the MMIO device shows up on the = platform. This works well if the MMIO device is really the same IP block = as a PCI device. This usually maps to the PCI BAR being the same thing = as the magic MMIO range. The =E2=80=9Cfake=E2=80=9D PCI IO Protocol also = abstracts platform specific DMA rules from the generic driver. >=20 > Slightly off-topic, but I've always been curious about this: given = that the entire purpose of PCI BARs is to allow for the use of = straightforward MMIO operations, in which standard CPU read/write = instructions can be used to access device registers with zero overhead = and no possible error conditions, why do the = EFI_PCI_IO_PROTOCOL.Mem.Read (and related) abstractions exist? They = seem to add a lot of complexity for negative benefit, and I'd be = interested to know if there was some reason why the design was chosen. >=20 Michael, Assuming physical address =3D=3D non-catchable memory region is not = always true. For example on Itainium you had to flip bit 63 in physical = mode to do a non-cached transaction. There are also some high end = servers that have different physical address ranges for PCI v.s DRAM.=20 Basically we were paranoid about portability. That and we really don=E2=80= =99t want #ifdef in the code for different architectures.=20 Thanks, Andrew Fish > Thanks, >=20 > Michael