* [PATCH] IntelSiliconPkg: Updated IgdOpregion.h based on latest spec
@ 2016-09-30 17:47 Giri P Mudusuru
2016-09-30 18:27 ` Ma, Maurice
0 siblings, 1 reply; 2+ messages in thread
From: Giri P Mudusuru @ 2016-09-30 17:47 UTC (permalink / raw)
To: edk2-devel; +Cc: Jiewen Yao, Michael Kinney, Maurice Ma, Amy Chan
Updated IgdOpregion.h to align with latest specification
https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
1) Updated Mailbox structures to align with latest spec
2) Added Mailbox 5 structure
3) Added defines for Signature and Mailbox support
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
---
.../Include/IndustryStandard/IgdOpRegion.h | 47 ++++++++++++++++------
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
index 7f76c09..4d5637c 100644
--- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
+++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
@@ -2,14 +2,7 @@
IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
Specification.
- https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf
-
- There are some mismatch between the specification and the implementation.
- The definition follows the latest implementation.
- 1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]
- 2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]
- 3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]
- 4) INTEL_IGD_OPREGION_VBT.RVBT[0x1800] Size is 6KB
+ https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
@@ -24,6 +17,13 @@
#ifndef _IGD_OPREGION_H_
#define _IGD_OPREGION_H_
+#define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"
+#define IGD_OPREGION_HEADER_MBOX1 BIT0
+#define IGD_OPREGION_HEADER_MBOX2 BIT1
+#define IGD_OPREGION_HEADER_MBOX3 BIT2
+#define IGD_OPREGION_HEADER_MBOX4 BIT3
+#define IGD_OPREGION_HEADER_MBOX5 BIT4
+
/**
OpRegion structures:
Sub-structures define the different parts of the OpRegion followed by the
@@ -49,7 +49,9 @@ typedef struct {
UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version
UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes
UINT32 DMOD; ///< Offset 0x5C Driver Model
- UINT8 RSV1[0xA0]; ///< Offset 0x60 Reserved
+ UINT32 PCON; ///< Offset 0x60 Platform Configuration
+ CHAR16 DVER[0x10] ///< Offset 0x64 GOP Version
+ UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero
} IGD_OPREGION_HEADER;
///
@@ -60,7 +62,7 @@ typedef struct {
UINT32 DRDY; ///< Offset 0x100 Driver Readiness
UINT32 CSTS; ///< Offset 0x104 Status
UINT32 CEVT; ///< Offset 0x108 Current Event
- UINT8 RSVD[0x14]; ///< Offset 0x10C Reserved Must be Zero
+ UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero
UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List
UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List
UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List
@@ -74,7 +76,9 @@ typedef struct {
UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL
UINT32 CNOT; ///< Offset 0x1BC Current OS Notification
UINT32 NRDY; ///< Offset 0x1C0 Driver Status
- UINT8 RSV3[0x3C]; ///< Offset 0x1C4 - 0x1FF Reserved
+ UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)
+ UINT8 CPD2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Devices List
+ UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero
} IGD_OPREGION_MBOX1;
///
@@ -85,7 +89,7 @@ typedef struct {
UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data
UINT32 PARM; ///< Offset 0x204 Software SCI Parameters
UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out
- UINT8 RSV4[0xF4]; ///< Offset 0x20C - 0x2FF Reserved
+ UINT8 RM21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero
} IGD_OPREGION_MBOX2;
///
@@ -106,7 +110,13 @@ typedef struct {
UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier
UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness
UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values
- UINT8 RSV5[0x62]; ///< Offset 0x39E - 0x3FF Reserved
+ UINT32 PCFT; ///< Offset 0x39E Power Conservation Features
+ UINT32 SROT; ///< Offset 0x3A2 Supported Rotation Angles
+ UINT32 IUER; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register
+ UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature
+ UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer
+ UINT32 STAT; ///< Offset 0x3B6 State Indicator
+ UINT8 RM31[0x45]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero
} IGD_OPREGION_MBOX3;
///
@@ -118,6 +128,16 @@ typedef struct {
} IGD_OPREGION_MBOX4;
///
+/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync
+/// Offset 0x1C00, Size 0x400
+///
+typedef struct {
+ UINT32 PHED; ///< Offset 0x1C00 Panel Header
+ UINT8 BDDC[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data)
+ UINT8 RM51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero
+} IGD_OPREGION_MBOX5;
+
+///
/// IGD OpRegion Structure
///
typedef struct {
@@ -126,6 +146,7 @@ typedef struct {
IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)
IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)
IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)
+ IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)
} IGD_OPREGION_STRUCTURE;
#pragma pack()
--
2.9.0.windows.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] IntelSiliconPkg: Updated IgdOpregion.h based on latest spec
2016-09-30 17:47 [PATCH] IntelSiliconPkg: Updated IgdOpregion.h based on latest spec Giri P Mudusuru
@ 2016-09-30 18:27 ` Ma, Maurice
0 siblings, 0 replies; 2+ messages in thread
From: Ma, Maurice @ 2016-09-30 18:27 UTC (permalink / raw)
To: edk2-devel@lists.01.org
Cc: Yao, Jiewen, Kinney, Michael D, Chan, Amy, Mudusuru, Giri P
Looks good to me.
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Thanks
Maurice
-----Original Message-----
From: Mudusuru, Giri P
Sent: Friday, September 30, 2016 10:47 AM
To: edk2-devel@lists.01.org
Cc: Yao, Jiewen; Kinney, Michael D; Ma, Maurice; Chan, Amy
Subject: [edk2] [PATCH] IntelSiliconPkg: Updated IgdOpregion.h based on latest spec
Updated IgdOpregion.h to align with latest specification https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
1) Updated Mailbox structures to align with latest spec
2) Added Mailbox 5 structure
3) Added defines for Signature and Mailbox support
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
---
.../Include/IndustryStandard/IgdOpRegion.h | 47 ++++++++++++++++------
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
index 7f76c09..4d5637c 100644
--- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
+++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
@@ -2,14 +2,7 @@
IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
Specification.
- https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf
-
- There are some mismatch between the specification and the implementation.
- The definition follows the latest implementation.
- 1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]
- 2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]
- 3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]
- 4) INTEL_IGD_OPREGION_VBT.RVBT[0x1800] Size is 6KB
+
+ https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.p
+ df
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials @@ -24,6 +17,13 @@ #ifndef _IGD_OPREGION_H_ #define _IGD_OPREGION_H_
+#define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"
+#define IGD_OPREGION_HEADER_MBOX1 BIT0
+#define IGD_OPREGION_HEADER_MBOX2 BIT1
+#define IGD_OPREGION_HEADER_MBOX3 BIT2
+#define IGD_OPREGION_HEADER_MBOX4 BIT3
+#define IGD_OPREGION_HEADER_MBOX5 BIT4
+
/**
OpRegion structures:
Sub-structures define the different parts of the OpRegion followed by the @@ -49,7 +49,9 @@ typedef struct {
UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version
UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes
UINT32 DMOD; ///< Offset 0x5C Driver Model
- UINT8 RSV1[0xA0]; ///< Offset 0x60 Reserved
+ UINT32 PCON; ///< Offset 0x60 Platform Configuration
+ CHAR16 DVER[0x10] ///< Offset 0x64 GOP Version
+ UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero
} IGD_OPREGION_HEADER;
///
@@ -60,7 +62,7 @@ typedef struct {
UINT32 DRDY; ///< Offset 0x100 Driver Readiness
UINT32 CSTS; ///< Offset 0x104 Status
UINT32 CEVT; ///< Offset 0x108 Current Event
- UINT8 RSVD[0x14]; ///< Offset 0x10C Reserved Must be Zero
+ UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero
UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List
UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List
UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List
@@ -74,7 +76,9 @@ typedef struct {
UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL
UINT32 CNOT; ///< Offset 0x1BC Current OS Notification
UINT32 NRDY; ///< Offset 0x1C0 Driver Status
- UINT8 RSV3[0x3C]; ///< Offset 0x1C4 - 0x1FF Reserved
+ UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)
+ UINT8 CPD2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Devices List
+ UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero
} IGD_OPREGION_MBOX1;
///
@@ -85,7 +89,7 @@ typedef struct {
UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data
UINT32 PARM; ///< Offset 0x204 Software SCI Parameters
UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out
- UINT8 RSV4[0xF4]; ///< Offset 0x20C - 0x2FF Reserved
+ UINT8 RM21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero
} IGD_OPREGION_MBOX2;
///
@@ -106,7 +110,13 @@ typedef struct {
UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier
UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness
UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values
- UINT8 RSV5[0x62]; ///< Offset 0x39E - 0x3FF Reserved
+ UINT32 PCFT; ///< Offset 0x39E Power Conservation Features
+ UINT32 SROT; ///< Offset 0x3A2 Supported Rotation Angles
+ UINT32 IUER; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register
+ UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature
+ UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer
+ UINT32 STAT; ///< Offset 0x3B6 State Indicator
+ UINT8 RM31[0x45]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero
} IGD_OPREGION_MBOX3;
///
@@ -118,6 +128,16 @@ typedef struct {
} IGD_OPREGION_MBOX4;
///
+/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS
+to Driver data sync /// Offset 0x1C00, Size 0x400 /// typedef struct {
+ UINT32 PHED; ///< Offset 0x1C00 Panel Header
+ UINT8 BDDC[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data)
+ UINT8 RM51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero
+} IGD_OPREGION_MBOX5;
+
+///
/// IGD OpRegion Structure
///
typedef struct {
@@ -126,6 +146,7 @@ typedef struct {
IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)
IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)
IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)
+ IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver
+ Notification Extension (Offset 0x1C00, Size 0x400)
} IGD_OPREGION_STRUCTURE;
#pragma pack()
--
2.9.0.windows.1
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