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From: "Tian, Feng" <feng.tian@intel.com>
To: "Ni, Ruiyu" <ruiyu.ni@intel.com>,
	"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "Tian, Feng" <feng.tian@intel.com>
Subject: Re: [PATCH] UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits
Date: Wed, 17 Aug 2016 05:50:00 +0000	[thread overview]
Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE5388237D5@SHSMSX101.ccr.corp.intel.com> (raw)
In-Reply-To: <20160815084119.95480-1-ruiyu.ni@intel.com>

Reviewed-by: Feng Tian <feng.tian@Intel.com>

Thanks
Feng

-----Original Message-----
From: Ni, Ruiyu 
Sent: Monday, August 15, 2016 4:41 PM
To: edk2-devel@lists.01.org
Cc: Tian, Feng <feng.tian@intel.com>
Subject: [PATCH] UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
---
 UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index a4702ed..4d4ade4 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -2092,7 +2092,7 @@ typedef union {
     ///
     /// [Bit 11] Valid Enable range mask.
     ///
-    UINT32  V:8;
+    UINT32  V:1;
     ///
     /// [Bits 31:12] PhysMask.  MTRR address range mask.
     ///
-- 
2.9.0.windows.1



      reply	other threads:[~2016-08-17  5:50 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-15  8:41 [PATCH] UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits Ruiyu Ni
2016-08-17  5:50 ` Tian, Feng [this message]

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