From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by ml01.01.org (Postfix) with ESMTP id E82801A1DF6 for ; Tue, 16 Aug 2016 22:50:04 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 16 Aug 2016 22:50:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,529,1464678000"; d="scan'208";a="1036923716" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 16 Aug 2016 22:50:06 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 16 Aug 2016 22:50:04 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 16 Aug 2016 22:50:03 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.8]) by shsmsx102.ccr.corp.intel.com ([169.254.2.147]) with mapi id 14.03.0248.002; Wed, 17 Aug 2016 13:50:01 +0800 From: "Tian, Feng" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" CC: "Tian, Feng" Thread-Topic: [PATCH] UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits Thread-Index: AQHR9tDVe3ax1SpBxEW66bOGIR23QKBMqLRg Date: Wed, 17 Aug 2016 05:50:00 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE5388237D5@SHSMSX101.ccr.corp.intel.com> References: <20160815084119.95480-1-ruiyu.ni@intel.com> In-Reply-To: <20160815084119.95480-1-ruiyu.ni@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Aug 2016 05:50:05 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Feng Tian Thanks Feng -----Original Message----- From: Ni, Ruiyu=20 Sent: Monday, August 15, 2016 4:41 PM To: edk2-devel@lists.01.org Cc: Tian, Feng Subject: [PATCH] UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead = of 8 bits Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Feng Tian --- UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/In= clude/Register/ArchitecturalMsr.h index a4702ed..4d4ade4 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -2092,7 +2092,7 @@ typedef union { /// /// [Bit 11] Valid Enable range mask. /// - UINT32 V:8; + UINT32 V:1; /// /// [Bits 31:12] PhysMask. MTRR address range mask. /// --=20 2.9.0.windows.1