From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B90801A1E56 for ; Tue, 13 Sep 2016 19:59:24 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP; 13 Sep 2016 19:59:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,332,1470726000"; d="scan'208";a="8050573" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga005.fm.intel.com with ESMTP; 13 Sep 2016 19:59:24 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 13 Sep 2016 19:59:23 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 13 Sep 2016 19:59:23 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.91]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.250]) with mapi id 14.03.0248.002; Wed, 14 Sep 2016 10:59:05 +0800 From: "Tian, Feng" To: "Zeng, Star" CC: "edk2-devel@lists.01.org" , "Tian, Feng" Thread-Topic: [patch] MdeModulePkg/Xhci: add 1ms delay before access MMIO reg during reset Thread-Index: AQHSDjPVc6190Yo6skaM4HhhFwq6sqB4S2kg Date: Wed, 14 Sep 2016 02:59:04 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE566D89102@SHSMSX101.ccr.corp.intel.com> References: <5a0c21d0fe889950fda9e59aaf2272b66d429b8f.1473816993.git.feng.tian@intel.com> <0C09AFA07DD0434D9E2A0C6AEB048310394BAD70@shsmsx102.ccr.corp.intel.com> In-Reply-To: <0C09AFA07DD0434D9E2A0C6AEB048310394BAD70@shsmsx102.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [patch] MdeModulePkg/Xhci: add 1ms delay before access MMIO reg during reset X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Sep 2016 02:59:24 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ok, I will update the commit title to highlight it's a change in XhciDxe. Thanks Feng -----Original Message----- From: Zeng, Star=20 Sent: Wednesday, September 14, 2016 10:58 AM To: Tian, Feng Cc: edk2-devel@lists.01.org Subject: RE: [patch] MdeModulePkg/Xhci: add 1ms delay before access MMIO re= g during reset How about to use XhciDxe instead of Xhci in the title to be more differenti= ated with another change in XhciPei? Reviewed-by: Star Zeng Thanks, Star -----Original Message----- From: Tian, Feng=20 Sent: Wednesday, September 14, 2016 9:37 AM To: Zeng, Star Cc: edk2-devel@lists.01.org Subject: [patch] MdeModulePkg/Xhci: add 1ms delay before access MMIO reg du= ring reset Some XHCI host controllers require to have extra 1ms delay before accessing= any MMIO register during HC reset. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian --- MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/= XhciDxe/XhciReg.c index d0f2205..cb822a6 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c @@ -2,7 +2,7 @@ =20 The XHCI register operation routines. =20 -Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -687,6 +68= 7,10 @@ XhcResetHC ( if ((Xhc->DebugCapSupOffset =3D=3D 0xFFFFFFFF) || ((XhcReadExtCapReg (Xh= c, Xhc->DebugCapSupOffset) & 0xFF) !=3D XHC_CAP_USB_DEBUG) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & B= IT0) =3D=3D 0)) { XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET); + // + // some XHCI host controllers require to have extra 1ms delay before a= ccessing any MMIO register during reset. + // + gBS->Stall (XHC_1_MILLISECOND); Status =3D XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, = FALSE, Timeout); } =20 -- 2.7.1.windows.2