From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1982881C6F for ; Wed, 23 Nov 2016 21:04:40 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 23 Nov 2016 21:04:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,690,1473145200"; d="scan'208";a="1089766040" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga002.fm.intel.com with ESMTP; 23 Nov 2016 21:04:39 -0800 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 23 Nov 2016 21:04:39 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 23 Nov 2016 21:04:39 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.239]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.142]) with mapi id 14.03.0248.002; Thu, 24 Nov 2016 13:04:35 +0800 From: "Tian, Feng" To: Marcin Wojtas , "edk2-devel@lists.01.org" CC: "ard.biesheuvel@linaro.org" , "leif.lindholm@linaro.org" , "Gao, Liming" , "Kinney, Michael D" , "Tian, Feng" Thread-Topic: [edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bit unconditionally for Ahci Thread-Index: AQHSRZnJnj4oQMVLp0SyBeMGUsOFQ6DnlInQ Date: Thu, 24 Nov 2016 05:04:35 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE566E53B4C@SHSMSX101.ccr.corp.intel.com> References: <1479913124-7869-1-git-send-email-mw@semihalf.com> In-Reply-To: <1479913124-7869-1-git-send-email-mw@semihalf.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bit unconditionally for Ahci X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Nov 2016 05:04:41 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Marcin I am ok with removing CAP.SAM check. But the logic will always set GHC.AE b= it. Shall we set GHC.AE only if it's 0? Thanks Feng -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Marc= in Wojtas Sent: Wednesday, November 23, 2016 10:59 PM To: edk2-devel@lists.01.org Cc: Tian, Feng ; ard.biesheuvel@linaro.org; leif.lindh= olm@linaro.org; Gao, Liming ; Kinney, Michael D Subject: [edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bit uncon= ditionally for Ahci According to AHCI Spec 1.3 GHC.AE bit description: "The implementation of this bit is dependent upon the value of the CAP.SAM = bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a re= set value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall h= ave a reset value of '1'." Being in AhciMode, for proper operation it is required, that GHC.AE bit is = always set, before any other AHCI registers are written to. Current AhciMod= e implementation, both in AhciReset() and AhciModeInitialization() function= s, set GHC.AE bit only depending on 'CAP.SAM =3D=3D 0' condition, assuming = (according to the AHCI spec), that otherwise it has to be set anyway. It ma= y however happen, that even if 'CAP.SAM =3D=3D 1', GHC.AE requires updating= by software. This patch enables setting GHC.AE bit unconditionally in AhciMode, which fi= xes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. The change = is transparent to all other platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Signed-off-by: Jan Dabros --- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePk= g/Bus/Ata/AtaAtapiPassThru/AhciMode.c index 533d201..6266ff3 100644 --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c @@ -1451,19 +1451,11 @@ AhciReset ( { UINT64 Delay; UINT32 Value; - UINT32 Capability; =20 // - // Collect AHCI controller information - // - Capability =3D AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); - =20 + // Enable AE before accessing any AHCI registers. // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode O= nly is not set - // - if ((Capability & EFI_AHCI_CAP_SAM) =3D=3D 0) { - AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); - } + AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); =20 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET); =20 @@ -2272,11 +2264,9 @@ AhciModeInitialization ( Capability =3D AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); =20 // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode O= nly is not set + // Enable AE before accessing any AHCI registers. // - if ((Capability & EFI_AHCI_CAP_SAM) =3D=3D 0) { - AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); - } + AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); =20 // // Enable 64-bit DMA support in the PCI layer if this controller -- 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel