From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AF03B81E68 for ; Thu, 24 Nov 2016 00:35:27 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP; 24 Nov 2016 00:35:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,690,1473145200"; d="scan'208";a="35032042" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga005.jf.intel.com with ESMTP; 24 Nov 2016 00:35:27 -0800 Received: from fmsmsx120.amr.corp.intel.com (10.18.124.208) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 24 Nov 2016 00:35:26 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx120.amr.corp.intel.com (10.18.124.208) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 24 Nov 2016 00:35:26 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.239]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.142]) with mapi id 14.03.0248.002; Thu, 24 Nov 2016 16:35:24 +0800 From: "Tian, Feng" To: Marcin Wojtas , "edk2-devel@lists.01.org" CC: "ard.biesheuvel@linaro.org" , "leif.lindholm@linaro.org" , "Gao, Liming" , "Kinney, Michael D" , "Tian, Feng" Thread-Topic: [edk2] [PATCH v2] MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci Thread-Index: AQHSRieth/he1QSoaECc5OyhT9Otp6Dnzubg Date: Thu, 24 Nov 2016 08:35:24 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE566E53C0C@SHSMSX101.ccr.corp.intel.com> References: <1479974073-29154-1-git-send-email-mw@semihalf.com> In-Reply-To: <1479974073-29154-1-git-send-email-mw@semihalf.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2] MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Nov 2016 08:35:27 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Feng Tian Do you want me to push it into EDKII trunk? Thanks Feng -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Marc= in Wojtas Sent: Thursday, November 24, 2016 3:55 PM To: edk2-devel@lists.01.org Cc: Tian, Feng ; ard.biesheuvel@linaro.org; leif.lindh= olm@linaro.org; Gao, Liming ; Kinney, Michael D Subject: [edk2] [PATCH v2] MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit= is always set in Ahci According to AHCI Spec 1.3 GHC.AE bit description: "The implementation of this bit is dependent upon the value of the CAP.SAM = bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a re= set value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall h= ave a reset value of '1'." Being in AhciMode, for proper operation it is required, that GHC.AE bit is = always set, before any other AHCI registers are written to. Current AhciMod= e implementation, both in AhciReset() and AhciModeInitialization() function= s, set GHC.AE bit only depending on 'CAP.SAM =3D=3D 0' condition, assuming = (according to the AHCI spec), that otherwise it has to be set anyway. It ma= y however happen, that even if 'CAP.SAM =3D=3D 1', GHC.AE requires updating= by software. This patch enables in AhciMode setting GHC.AE in case its initial value is = '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. T= he change is transparent to all other platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Signed-off-by: Jan Dabros --- Changelog: v1 -> v2 * Instead of doing it uncoditionally, enable setting GHC.AE bit only in case its initial value is '0' --- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 21 ++++++++++----------= - 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePk= g/Bus/Ata/AtaAtapiPassThru/AhciMode.c index 533d201..4d01c1d 100644 --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c @@ -1451,17 +1451,13 @@ AhciReset ( { UINT64 Delay; UINT32 Value; - UINT32 Capability; =20 // - // Collect AHCI controller information - // - Capability =3D AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); - - // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode O= nly is not set + // Make sure that GHC.AE bit is set before accessing any AHCI registers. // - if ((Capability & EFI_AHCI_CAP_SAM) =3D=3D 0) { + Value =3D AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET); + + if ((Value & EFI_AHCI_GHC_ENABLE) =3D=3D 0) { AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); } =20 @@ -2252,6 +2248,7 @@ AhciModeInitialization ( EFI_ATA_COLLECTIVE_MODE *SupportedModes; EFI_ATA_TRANSFER_MODE TransferMode; UINT32 PhyDetectDelay; + UINT32 Value; =20 if (Instance =3D=3D NULL) { return EFI_INVALID_PARAMETER; @@ -2270,11 +2267,13 @@ AhciModeInitialization ( // Collect AHCI controller information // Capability =3D AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); - =20 + // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode O= nly is not set + // Make sure that GHC.AE bit is set before accessing any AHCI registers. // - if ((Capability & EFI_AHCI_CAP_SAM) =3D=3D 0) { + Value =3D AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET); + + if ((Value & EFI_AHCI_GHC_ENABLE) =3D=3D 0) { AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); } =20 -- 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel