* [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD
@ 2016-11-30 7:06 Michael Kinney
2016-11-30 7:06 ` [Patch 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure Michael Kinney
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Michael Kinney @ 2016-11-30 7:06 UTC (permalink / raw)
To: edk2-devel; +Cc: Jiewen Yao, Jeff Fan, Feng Tian
https://bugzilla.tianocore.org/show_bug.cgi?id=277
Remove MtrrBaseMaskPtr field from PSD and move MTRR to a
global variable since all CPUs use the same MTRR settings.
Reduce use of PSD to allow alternate SmmCpuFeaturesLib
implementations to use their own PSD layouts.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Michael Kinney (2):
UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure
UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 33 ++++--------------
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 15 ++++----
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 26 --------------
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 2 +-
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 40 +++++++++++++++++++++-
8 files changed, 64 insertions(+), 61 deletions(-)
--
2.6.3.windows.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Patch 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure
2016-11-30 7:06 [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD Michael Kinney
@ 2016-11-30 7:06 ` Michael Kinney
2016-11-30 7:06 ` [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions Michael Kinney
2016-12-01 4:58 ` [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD Fan, Jeff
2 siblings, 0 replies; 5+ messages in thread
From: Michael Kinney @ 2016-11-30 7:06 UTC (permalink / raw)
To: edk2-devel; +Cc: Jiewen Yao, Jeff Fan, Feng Tian
https://bugzilla.tianocore.org/show_bug.cgi?id=277
All CPUs use the same MTRR settings. Move MTRR settings
from a field in the PROCESSOR_SMM_DESCRIPTOR structure into
a module global variable.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 18 ++++--------------
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 +-
2 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index cfbf59e..6dc9607 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -17,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
// Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
//
-UINT64 gSmiMtrrs[MTRR_NUMBER_OF_FIXED_MTRR + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
+MTRR_SETTINGS gSmiMtrrs;
UINT64 gPhyMask;
SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL;
UINTN mSmmMpSyncDataSize;
@@ -283,20 +283,12 @@ ReplaceOSMtrrs (
IN UINTN CpuIndex
)
{
- PROCESSOR_SMM_DESCRIPTOR *Psd;
- UINT64 *SmiMtrrs;
- MTRR_SETTINGS *BiosMtrr;
-
- Psd = (PROCESSOR_SMM_DESCRIPTOR*)(mCpuHotPlugData.SmBase[CpuIndex] + SMM_PSD_OFFSET);
- SmiMtrrs = (UINT64*)(UINTN)Psd->MtrrBaseMaskPtr;
-
SmmCpuFeaturesDisableSmrr ();
//
// Replace all MTRRs registers
//
- BiosMtrr = (MTRR_SETTINGS*)SmiMtrrs;
- MtrrSetAllMtrrs(BiosMtrr);
+ MtrrSetAllMtrrs (&gSmiMtrrs);
}
/**
@@ -1376,7 +1368,6 @@ InitializeMpServiceData (
{
UINT32 Cr3;
UINTN Index;
- MTRR_SETTINGS *Mtrr;
PROCESSOR_SMM_DESCRIPTOR *Psd;
UINT8 *GdtTssTables;
UINTN GdtTableStepSize;
@@ -1439,9 +1430,8 @@ InitializeMpServiceData (
//
// Record current MTRR settings
//
- ZeroMem(gSmiMtrrs, sizeof (gSmiMtrrs));
- Mtrr = (MTRR_SETTINGS*)gSmiMtrrs;
- MtrrGetAllMtrrs (Mtrr);
+ ZeroMem (&gSmiMtrrs, sizeof (gSmiMtrrs));
+ MtrrGetAllMtrrs (&gSmiMtrrs);
return Cr3;
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index abe5cc6..bd6abf2 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -380,7 +380,7 @@ typedef struct {
UINT16 Reserved11; // Offset 0x50
UINT16 Reserved12; // Offset 0x52
UINT32 Reserved13; // Offset 0x54
- UINT64 MtrrBaseMaskPtr; // Offset 0x58
+ UINT64 Reserved14; // Offset 0x58
} PROCESSOR_SMM_DESCRIPTOR;
--
2.6.3.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions
2016-11-30 7:06 [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD Michael Kinney
2016-11-30 7:06 ` [Patch 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure Michael Kinney
@ 2016-11-30 7:06 ` Michael Kinney
2016-12-01 4:58 ` [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD Fan, Jeff
2 siblings, 0 replies; 5+ messages in thread
From: Michael Kinney @ 2016-11-30 7:06 UTC (permalink / raw)
To: edk2-devel; +Cc: Jiewen Yao, Jeff Fan, Feng Tian
https://bugzilla.tianocore.org/show_bug.cgi?id=277
Remove dependency on layout of PROCESSOR_SMM_DESCRIPTOR
everywhere possible. The only exception is the standard
SMI entry handler template that is included with the
PiSmmCpuDxeSmm module. This allows an instance of the
SmmCpuFeaturesLib to provide alternate
PROCESSOR_SMM_DESCRIPTOR structure layouts.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 15 ++------
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 15 ++++----
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 26 --------------
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 2 +-
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 40 +++++++++++++++++++++-
8 files changed, 60 insertions(+), 47 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index 0c07558..378e065 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -31,6 +31,9 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
.equ MSR_EFER, 0xc0000080
.equ MSR_EFER_XD, 0x800
+#
+# Constants relating to PROCESSOR_SMM_DESCRIPTOR
+#
.equ DSC_OFFSET, 0xfb00
.equ DSC_GDTPTR, 0x30
.equ DSC_GDTSIZ, 0x38
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
index eda1708..a4f4dcb 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
@@ -26,6 +26,9 @@ MSR_IA32_MISC_ENABLE EQU 1A0h
MSR_EFER EQU 0c0000080h
MSR_EFER_XD EQU 0800h
+;
+; Constants relating to PROCESSOR_SMM_DESCRIPTOR
+;
DSC_OFFSET EQU 0fb00h
DSC_GDTPTR EQU 30h
DSC_GDTSIZ EQU 38h
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index d50a317..4d2383f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -22,6 +22,9 @@
%define MSR_EFER 0xc0000080
%define MSR_EFER_XD 0x800
+;
+; Constants relating to PROCESSOR_SMM_DESCRIPTOR
+;
%define DSC_OFFSET 0xfb00
%define DSC_GDTPTR 0x30
%define DSC_GDTSIZ 0x38
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 6dc9607..35bd37c 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1368,7 +1368,6 @@ InitializeMpServiceData (
{
UINT32 Cr3;
UINTN Index;
- PROCESSOR_SMM_DESCRIPTOR *Psd;
UINT8 *GdtTssTables;
UINTN GdtTableStepSize;
@@ -1403,24 +1402,16 @@ InitializeMpServiceData (
GdtTssTables = InitGdt (Cr3, &GdtTableStepSize);
//
- // Initialize PROCESSOR_SMM_DESCRIPTOR for each CPU
+ // Install SMI handler for each CPU
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
- Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(mCpuHotPlugData.SmBase[Index] + SMM_PSD_OFFSET);
- CopyMem (Psd, &gcPsd, sizeof (gcPsd));
- Psd->SmmGdtPtr = (UINT64)(UINTN)(GdtTssTables + GdtTableStepSize * Index);
- Psd->SmmGdtSize = gcSmiGdtr.Limit + 1;
-
- //
- // Install SMI handler
- //
InstallSmiHandler (
Index,
(UINT32)mCpuHotPlugData.SmBase[Index],
(VOID*)((UINTN)Stacks + (StackSize * Index)),
StackSize,
- (UINTN)Psd->SmmGdtPtr,
- Psd->SmmGdtSize,
+ (UINTN)(GdtTssTables + GdtTableStepSize * Index),
+ gcSmiGdtr.Limit + 1,
gcSmiIdtr.Base,
gcSmiIdtr.Limit + 1,
Cr3
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index f957de1..4bef60a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -711,22 +711,23 @@ PiCpuSmmEntry (
//
// Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
- // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
- // is rounded up to nearest power of 2.
+ // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
+ // This size is rounded up to nearest power of 2.
//
TileCodeSize = GetSmiHandlerSize ();
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
- TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);
+ TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
//
- // If the TileSize is larger than space available for the SMI Handler of CPU[i],
- // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
- // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
- // reduced.
+ // If the TileSize is larger than space available for the SMI Handler of
+ // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save
+ // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then
+ // the SMI Handler size must be reduced or the size of the extra CPU specific
+ // context must be reduced.
//
ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index bd6abf2..611cbc1 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -359,31 +359,6 @@ typedef struct {
#define SMM_PSD_OFFSET 0xfb00
-typedef struct {
- UINT64 Signature; // Offset 0x00
- UINT16 Reserved1; // Offset 0x08
- UINT16 Reserved2; // Offset 0x0A
- UINT16 Reserved3; // Offset 0x0C
- UINT16 SmmCs; // Offset 0x0E
- UINT16 SmmDs; // Offset 0x10
- UINT16 SmmSs; // Offset 0x12
- UINT16 SmmOtherSegment; // Offset 0x14
- UINT16 Reserved4; // Offset 0x16
- UINT64 Reserved5; // Offset 0x18
- UINT64 Reserved6; // Offset 0x20
- UINT64 Reserved7; // Offset 0x28
- UINT64 SmmGdtPtr; // Offset 0x30
- UINT32 SmmGdtSize; // Offset 0x38
- UINT32 Reserved8; // Offset 0x3C
- UINT64 Reserved9; // Offset 0x40
- UINT64 Reserved10; // Offset 0x48
- UINT16 Reserved11; // Offset 0x50
- UINT16 Reserved12; // Offset 0x52
- UINT32 Reserved13; // Offset 0x54
- UINT64 Reserved14; // Offset 0x58
-} PROCESSOR_SMM_DESCRIPTOR;
-
-
///
/// All global semaphores' pointer
///
@@ -427,7 +402,6 @@ extern EFI_PHYSICAL_ADDRESS mGdtBuffer;
extern UINTN mGdtBufferSize;
extern IA32_DESCRIPTOR gcSmiIdtr;
extern VOID *gcSmiIdtrPtr;
-extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
extern UINT64 gPhyMask;
extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;
extern UINTN mSmmStackArrayBase;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index c85e025..bcda53b 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -684,7 +684,7 @@ PatchSmmSaveStateMap (
TileCodeSize = GetSmiHandlerSize ();
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
- TileDataSize = sizeof (SMRAM_SAVE_STATE_MAP) + sizeof (PROCESSOR_SMM_DESCRIPTOR);
+ TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index 539c029..c37e9e8 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -1,7 +1,7 @@
/** @file
Provides services to access SMRAM Save State Map
-Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -23,6 +23,34 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Register/Cpuid.h>
#include <Register/SmramSaveStateMap.h>
+#include "PiSmmCpuDxeSmm.h"
+
+typedef struct {
+ UINT64 Signature; // Offset 0x00
+ UINT16 Reserved1; // Offset 0x08
+ UINT16 Reserved2; // Offset 0x0A
+ UINT16 Reserved3; // Offset 0x0C
+ UINT16 SmmCs; // Offset 0x0E
+ UINT16 SmmDs; // Offset 0x10
+ UINT16 SmmSs; // Offset 0x12
+ UINT16 SmmOtherSegment; // Offset 0x14
+ UINT16 Reserved4; // Offset 0x16
+ UINT64 Reserved5; // Offset 0x18
+ UINT64 Reserved6; // Offset 0x20
+ UINT64 Reserved7; // Offset 0x28
+ UINT64 SmmGdtPtr; // Offset 0x30
+ UINT32 SmmGdtSize; // Offset 0x38
+ UINT32 Reserved8; // Offset 0x3C
+ UINT64 Reserved9; // Offset 0x40
+ UINT64 Reserved10; // Offset 0x48
+ UINT16 Reserved11; // Offset 0x50
+ UINT16 Reserved12; // Offset 0x52
+ UINT32 Reserved13; // Offset 0x54
+ UINT64 Reserved14; // Offset 0x58
+} PROCESSOR_SMM_DESCRIPTOR;
+
+extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
+
//
// EFER register LMA bit
//
@@ -657,6 +685,8 @@ InstallSmiHandler (
IN UINT32 Cr3
)
{
+ PROCESSOR_SMM_DESCRIPTOR *Psd;
+
if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {
//
// Install SMI handler provided by library
@@ -676,6 +706,14 @@ InstallSmiHandler (
}
//
+ // Initialize PROCESSOR_SMM_DESCRIPTOR
+ //
+ Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(SmBase + SMM_PSD_OFFSET);
+ CopyMem (Psd, &gcPsd, sizeof (gcPsd));
+ Psd->SmmGdtPtr = (UINT64)GdtBase;
+ Psd->SmmGdtSize = (UINT32)GdtSize;
+
+ //
// Initialize values in template before copy
//
gSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
--
2.6.3.windows.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD
2016-11-30 7:06 [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD Michael Kinney
2016-11-30 7:06 ` [Patch 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure Michael Kinney
2016-11-30 7:06 ` [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions Michael Kinney
@ 2016-12-01 4:58 ` Fan, Jeff
2016-12-01 4:59 ` Tian, Feng
2 siblings, 1 reply; 5+ messages in thread
From: Fan, Jeff @ 2016-12-01 4:58 UTC (permalink / raw)
To: Kinney, Michael D, edk2-devel@lists.01.org; +Cc: Yao, Jiewen, Tian, Feng
Reviewed-by: Jeff Fan <jeff.fan@intel.com> on serials.
-----Original Message-----
From: Kinney, Michael D
Sent: Wednesday, November 30, 2016 3:07 PM
To: edk2-devel@lists.01.org
Cc: Yao, Jiewen; Fan, Jeff; Tian, Feng
Subject: [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD
https://bugzilla.tianocore.org/show_bug.cgi?id=277
Remove MtrrBaseMaskPtr field from PSD and move MTRR to a global variable since all CPUs use the same MTRR settings.
Reduce use of PSD to allow alternate SmmCpuFeaturesLib implementations to use their own PSD layouts.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Michael Kinney (2):
UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure
UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 33 ++++--------------
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 15 ++++----
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 26 --------------
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 2 +-
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 40 +++++++++++++++++++++-
8 files changed, 64 insertions(+), 61 deletions(-)
--
2.6.3.windows.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD
2016-12-01 4:58 ` [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD Fan, Jeff
@ 2016-12-01 4:59 ` Tian, Feng
0 siblings, 0 replies; 5+ messages in thread
From: Tian, Feng @ 2016-12-01 4:59 UTC (permalink / raw)
To: Fan, Jeff, Kinney, Michael D, edk2-devel@lists.01.org
Cc: Yao, Jiewen, Tian, Feng
Reviewed-by: Feng Tian <feng.tian@Intel.com>
Thanks
Feng
-----Original Message-----
From: Fan, Jeff
Sent: Thursday, December 1, 2016 12:58 PM
To: Kinney, Michael D <michael.d.kinney@intel.com>; edk2-devel@lists.01.org
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Tian, Feng <feng.tian@intel.com>
Subject: RE: [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD
Reviewed-by: Jeff Fan <jeff.fan@intel.com> on serials.
-----Original Message-----
From: Kinney, Michael D
Sent: Wednesday, November 30, 2016 3:07 PM
To: edk2-devel@lists.01.org
Cc: Yao, Jiewen; Fan, Jeff; Tian, Feng
Subject: [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD
https://bugzilla.tianocore.org/show_bug.cgi?id=277
Remove MtrrBaseMaskPtr field from PSD and move MTRR to a global variable since all CPUs use the same MTRR settings.
Reduce use of PSD to allow alternate SmmCpuFeaturesLib implementations to use their own PSD layouts.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Michael Kinney (2):
UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure
UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 3 ++
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 33 ++++--------------
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 15 ++++----
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 26 --------------
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 2 +-
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 40 +++++++++++++++++++++-
8 files changed, 64 insertions(+), 61 deletions(-)
--
2.6.3.windows.1
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-12-01 4:59 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-11-30 7:06 [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD Michael Kinney
2016-11-30 7:06 ` [Patch 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure Michael Kinney
2016-11-30 7:06 ` [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions Michael Kinney
2016-12-01 4:58 ` [Patch 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reduce use of PSD Fan, Jeff
2016-12-01 4:59 ` Tian, Feng
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox