From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A70EB81851 for ; Fri, 6 Jan 2017 00:42:59 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP; 06 Jan 2017 00:42:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,323,1477983600"; d="scan'208";a="1108759259" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga002.fm.intel.com with ESMTP; 06 Jan 2017 00:42:59 -0800 Received: from fmsmsx121.amr.corp.intel.com (10.18.125.36) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 6 Jan 2017 00:42:59 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx121.amr.corp.intel.com (10.18.125.36) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 6 Jan 2017 00:42:58 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.177]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.132]) with mapi id 14.03.0248.002; Fri, 6 Jan 2017 16:42:57 +0800 From: "Tian, Feng" To: Haojian Zhuang , "leif.lindholm@linaro.org" , "ard.biesheuvel@linaro.org" , "edk2-devel@lists.01.org" CC: "Tian, Feng" Thread-Topic: [PATCH 8/9] Ufs: fix to add cache operation Thread-Index: AQHSZ+mPWAiW3/CSpk+qLhVNktkqyaErIXWw Date: Fri, 6 Jan 2017 08:42:56 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE5699A60DD@SHSMSX101.ccr.corp.intel.com> References: <1483685538-11058-1-git-send-email-haojian.zhuang@linaro.org> <1483685538-11058-9-git-send-email-haojian.zhuang@linaro.org> In-Reply-To: <1483685538-11058-9-git-send-email-haojian.zhuang@linaro.org> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 8/9] Ufs: fix to add cache operation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Jan 2017 08:42:59 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Haojian, The CmdDescHost is a EdkiiUfsHcOperationBusMasterCommonBuffer common buffer= , which means Host and DMA could access this region at the same time. So th= ere is no cache coherent issue:) Thanks Feng -----Original Message----- From: Haojian Zhuang [mailto:haojian.zhuang@linaro.org]=20 Sent: Friday, January 6, 2017 2:52 PM To: Tian, Feng ; leif.lindholm@linaro.org; ard.biesheu= vel@linaro.org; edk2-devel@lists.01.org Cc: Haojian Zhuang Subject: [PATCH 8/9] Ufs: fix to add cache operation Since command UPIU is initialized with virtual address that CPU accesses, n= eed to add cache operation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang --- MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h | 1 + MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf | 1 + MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c | 8 ++++++++ 3 files changed, 10 insertions(+) diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h b/MdeModuleP= kg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h index 7fc82ba..af13757 100644 --- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h +++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThru.h @@ -26,6 +26,7 @@ #include #include #include +#include #include #include =20 diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf b/MdeMo= dulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf index c90c72f..254f51a 100644 --- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf +++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruDxe.inf @@ -49,6 +49,7 @@ BaseMemoryLib UefiLib BaseLib + CacheMaintenanceLib UefiDriverEntryPoint DebugLib DevicePathLib diff --git a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c b/MdeModu= lePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c index db70fb1..98a17ac 100644 --- a/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c +++ b/MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci.c @@ -1449,6 +1449,7 @@ UfsExecScsiCmds ( UTP_TR_PRD *PrdtBase; EFI_TPL OldTpl; UFS_PASS_THRU_TRANS_REQ *TransReq; + UINTN TotalLen; =20 TransReq =3D AllocateZeroPool (sizeof (UFS_PASS_THRU_TRANS_REQ)); if (TransReq =3D=3D NULL) { @@ -1521,6 +1522,13 @@ UfsExecScsiCmds ( UfsInitUtpPrdt (PrdtBase, (VOID*)(UINTN)DataBufPhyAddr, DataLen); =20 // + // Flush & invalidate data cache since CmdDescHost is virtual address =20 + // and Command UPIU is updated after Map (). + // + TotalLen =3D (TransReq->Trd->PrdtO << 2) + (TransReq->Trd->PrdtL << 2); = =20 + WriteBackInvalidateDataCacheRange (TransReq->CmdDescHost, TotalLen); + + // // Insert the async SCSI cmd to the Async I/O list // if (Event !=3D NULL) { -- 2.7.4