From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DBB1A81F40 for ; Sun, 26 Feb 2017 22:44:44 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP; 26 Feb 2017 22:44:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,213,1484035200"; d="scan'208";a="1135317064" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga002.fm.intel.com with ESMTP; 26 Feb 2017 22:44:44 -0800 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 26 Feb 2017 22:44:44 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 26 Feb 2017 22:44:43 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.177]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0248.002; Mon, 27 Feb 2017 14:44:41 +0800 From: "Tian, Feng" To: "Fan, Jeff" , "edk2-devel@lists.01.org" CC: Leo Duran , "Kinney, Michael D" , "Tian, Feng" Thread-Topic: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Remove used SetCacheability() Thread-Index: AQHSkLq/7oCXyBsY7UKAuIseDK47HKF8aG/g Date: Mon, 27 Feb 2017 06:44:41 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE5699B598A@SHSMSX101.ccr.corp.intel.com> References: <20170227053114.5452-1-jeff.fan@intel.com> In-Reply-To: <20170227053114.5452-1-jeff.fan@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Remove used SetCacheability() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 06:44:45 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Feng Tian Thanks Feng -----Original Message----- From: Fan, Jeff=20 Sent: Monday, February 27, 2017 1:31 PM To: edk2-devel@lists.01.org Cc: Leo Duran ; Tian, Feng ; Kinney= , Michael D Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Remove used SetCacheability() No one uses the internal function SetCacheability(). https://bugzilla.tianocore.org/show_bug.cgi?id=3D400 This updating is suggested by Leo' comments at https://www.mail-archive.com= /edk2-devel@lists.01.org/msg22634.html Cc: Leo Duran Cc: Feng Tian Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 70 +------------------------------= ---- 1 file changed, 1 insertion(+), 69 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index c7aa48b..b180b14 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1,7 +1,7 @@ /** @file SMM MP service implementation =20 -Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -827,74 +8= 27,6 @@ Gen4GPageTable ( } =20 /** - Set memory cache ability. - - @param PageTable PageTable Address - @param Address Memory Address to change cache ability - @param Cacheability Cache ability to set - -**/ -VOID -SetCacheability ( - IN UINT64 *PageTable, - IN UINTN Address, - IN UINT8 Cacheability - ) -{ - UINTN PTIndex; - VOID *NewPageTableAddress; - UINT64 *NewPageTable; - UINTN Index; - - ASSERT ((Address & EFI_PAGE_MASK) =3D=3D 0); - - if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { - PTIndex =3D (UINTN)RShiftU64 (Address, 39) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - } - - PTIndex =3D (UINTN)RShiftU64 (Address, 30) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - - // - // A perfect implementation should check the original cacheability with = the - // one being set, and break a 2M page entry into pieces only when they - // disagreed. - // - PTIndex =3D (UINTN)RShiftU64 (Address, 21) & 0x1ff; - if ((PageTable[PTIndex] & IA32_PG_PS) !=3D 0) { - // - // Allocate a page from SMRAM - // - NewPageTableAddress =3D AllocatePageTableMemory (1); - ASSERT (NewPageTableAddress !=3D NULL); - - NewPageTable =3D (UINT64 *)NewPageTableAddress; - - for (Index =3D 0; Index < 0x200; Index++) { - NewPageTable[Index] =3D PageTable[PTIndex]; - if ((NewPageTable[Index] & IA32_PG_PAT_2M) !=3D 0) { - NewPageTable[Index] &=3D ~((UINT64)IA32_PG_PAT_2M); - NewPageTable[Index] |=3D (UINT64)IA32_PG_PAT_4K; - } - NewPageTable[Index] |=3D (UINT64)(Index << EFI_PAGE_SHIFT); - } - - PageTable[PTIndex] =3D ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_= ATTRIBUTE_BITS; - } - - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - - PTIndex =3D (UINTN)RShiftU64 (Address, 12) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable[PTIndex] &=3D ~((UINT64)((IA32_PG_PAT_4K | IA32_PG_CD | IA32_P= G_WT))); - PageTable[PTIndex] |=3D (UINT64)Cacheability; -} - -/** Schedule a procedure to run on the specified CPU. =20 @param[in] Procedure The address of the procedure t= o run -- 2.9.3.windows.2