From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A1B78802A0 for ; Thu, 16 Mar 2017 19:54:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1489719296; x=1521255296; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=OSuhCehKpeop7nQb2KFhM42tFI/tWphtt1h1Xi/XO/4=; b=Y8DMcvALq2i/Vs7VlgD3XZ0NNWS+f4SMYzOz3RKKpi+rK4+RRKQbA5XY wpZFtoDMc6sJ4OiANFzAMp5rWHFL8Q==; Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Mar 2017 19:54:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,175,1486454400"; d="scan'208";a="237341037" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga004.fm.intel.com with ESMTP; 16 Mar 2017 19:54:55 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 16 Mar 2017 19:54:56 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 16 Mar 2017 19:54:55 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.177]) by SHSMSX103.ccr.corp.intel.com ([10.239.4.69]) with mapi id 14.03.0248.002; Fri, 17 Mar 2017 10:54:53 +0800 From: "Tian, Feng" To: "Fan, Jeff" , "edk2-devel@lists.01.org" CC: Anthony PERARD , "Yao, Jiewen" , "Tian, Feng" Thread-Topic: [edk2] [PATCH] UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE check Thread-Index: AQHSnS8fxXAp1YkKlEalNbEkWT2My6GYWUfQ Date: Fri, 17 Mar 2017 02:54:53 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE5699BB417@SHSMSX101.ccr.corp.intel.com> References: <20170315015430.4800-1-jeff.fan@intel.com> In-Reply-To: <20170315015430.4800-1-jeff.fan@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE check X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Mar 2017 02:54:56 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Feng Tian Thanks Feng -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jeff= Fan Sent: Wednesday, March 15, 2017 9:55 AM To: edk2-devel@lists.01.org Cc: Anthony PERARD ; Tian, Feng ; Yao, Jiewen Subject: [edk2] [PATCH] UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE chec= k The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processo= rs. Because reading CPUID.80000001H:EDK[20] is enough to check if XD feature is= supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0). Cc: Anthony PERARD Cc: Jiewen Yao Cc: Feng Tian Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/CpuDxe/CpuPageTable.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.c index 65f607a..ab664b4 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -193,12 +193,9 @@ GetCurrentPagingContext ( AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); if ((RegEdx & BIT20) !=3D 0) { // XD supported - if ((AsmReadMsr64 (0x000001A0) & BIT34) =3D=3D 0) { - // XD enabled - if ((AsmReadMsr64 (0xC0000080) & BIT11) !=3D 0) { - // XD activated - PagingContext->ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_P= AGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED; - } + if ((AsmReadMsr64 (0xC0000080) & BIT11) !=3D 0) { + // XD activated + PagingContext->ContextData.Ia32.Attributes |=3D=20 + PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED; } } if ((RegEdx & BIT26) !=3D 0) { -- 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel