From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A301421BC6A7F for ; Sun, 26 Mar 2017 22:30:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490592629; x=1522128629; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=uFV3jdYOA7rS94RnsKdk88EPb68cRZ2fPQmSzsWWkuQ=; b=LVgMbdwuBoBgfAWlDiXrJ6JEsgTsLhiQZL2l8J77uuByi0mFsBgObkep oooMcsIMC+b+AGcnw0tmzzhWGKfaHQ==; Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Mar 2017 22:30:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,229,1486454400"; d="scan'208";a="65365834" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 26 Mar 2017 22:30:29 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 26 Mar 2017 22:30:28 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.224]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.253]) with mapi id 14.03.0248.002; Mon, 27 Mar 2017 13:30:27 +0800 From: "Tian, Feng" To: "Fan, Jeff" , "edk2-devel@lists.01.org" CC: "Tian, Feng" Thread-Topic: [edk2] [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table Thread-Index: AQHSo5Y7/6mpHWKwj0+jz8DOT164L6GoL0SA Date: Mon, 27 Mar 2017 05:30:26 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE5699CF1E9@SHSMSX101.ccr.corp.intel.com> References: <20170323052738.10888-1-jeff.fan@intel.com> In-Reply-To: <20170323052738.10888-1-jeff.fan@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Mar 2017 05:30:29 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Series Reviewed-by: Feng Tian Thanks Feng -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Fan,= Jeff Sent: Thursday, March 23, 2017 1:28 PM To: edk2-devel@lists.01.org Subject: [edk2] [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU = Register Table The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to= indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 t= ype actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB. https://bugzilla.tianocore.org/show_bug.cgi?id=3D347 Jeff Fan (2): UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64 UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address UefiCpuPkg/Include/AcpiCpuData.h | 12 +++++++-= ---- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 4 ++-- .../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 6 +++--- .../Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 9 +++++---= - UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 2 +- 5 files changed, 18 insertions(+), 15 deletions(-) -- 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel