From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C27F521A18AAA for ; Mon, 27 Mar 2017 18:42:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490665330; x=1522201330; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=GvesvtlqROjrfikOX+06cNHV2Hg6PLvo3z0eGvHh2oE=; b=vUr5Y9pEajJdHUtFbuGGTm7SuMlYU37JRAU3QZJdN5hRFnk3iJeWncv3 tv1rcwMKWNCmDsy4yy+dRrRI1j9OHA==; Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Mar 2017 18:42:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,234,1486454400"; d="scan'208";a="1112774828" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga001.jf.intel.com with ESMTP; 27 Mar 2017 18:42:10 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Mar 2017 18:42:10 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Mar 2017 18:42:09 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.224]) by shsmsx102.ccr.corp.intel.com ([169.254.2.212]) with mapi id 14.03.0248.002; Tue, 28 Mar 2017 09:42:06 +0800 From: "Tian, Feng" To: "Fan, Jeff" , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" , "Tian, Feng" Thread-Topic: [PATCH v2] UefiCpuPkg/MpLib.c: Add checking CR0 PG bit Thread-Index: AQHSp14sB4polj8zGESY1YFx/gXnuqGpefEg Date: Tue, 28 Mar 2017 01:42:05 +0000 Message-ID: <7F1BAD85ADEA444D97065A60D2E97EE5699CF666@SHSMSX101.ccr.corp.intel.com> References: <20170328005635.20988-1-jeff.fan@intel.com> In-Reply-To: <20170328005635.20988-1-jeff.fan@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2] UefiCpuPkg/MpLib.c: Add checking CR0 PG bit X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Mar 2017 01:42:10 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Feng Tian Thanks Feng -----Original Message----- From: Fan, Jeff=20 Sent: Tuesday, March 28, 2017 8:57 AM To: edk2-devel@lists.01.org Cc: Tian, Feng ; Kinney, Michael D Subject: [PATCH v2] UefiCpuPkg/MpLib.c: Add checking CR0 PG bit If CR0 PG bit is not set, it means paging is not enabled on BSP. Thus, Exec= ute Disable feature is not working actually. Thus, we cannot enable it on A= Ps. v2: Correct the commit log. Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 38 +++++++++++++++++++++++---------= ---- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 55fe812..bb93526 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1,7 +1,7 @@ /** @file CPU MP Initialize Library common functions. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights=20 + reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -18,8 +18,11 @@ EFI_GUID mCpuInitMpLibHobGuid =3D CPU_INIT_MP= _LIB_HOB_GUID; =20 /** The function will check if BSP Execute Disable is enabled. - DxeIpl may have enabled Execute Disable for BSP, - APs need to get the status and sync up the settings. + + DxeIpl may have enabled Execute Disable for BSP, APs need to get the=20 + status and sync up the settings. + If BSP's CR0.Paging is not set, BSP execute Disble feature is not=20 + working actually. =20 @retval TRUE BSP Execute Disable is enabled. @retval FALSE BSP Execute Disable is not enabled. @@ -33,23 +36,30 @@ IsBspExecuteDisableEnabled ( CPUID_EXTENDED_CPU_SIG_EDX Edx; MSR_IA32_EFER_REGISTER EferMsr; BOOLEAN Enabled; + IA32_CR0 Cr0; =20 Enabled =3D FALSE; - AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); - if (Eax >=3D CPUID_EXTENDED_CPU_SIG) { - AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32); + Cr0.UintN =3D AsmReadCr0 (); + if (Cr0.Bits.PG !=3D 0) { // - // CPUID 0x80000001 - // Bit 20: Execute Disable Bit available. + // If CR0 Paging bit is set // - if (Edx.Bits.NX !=3D 0) { - EferMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); + AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); + if (Eax >=3D CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32); // - // MSR 0xC0000080 - // Bit 11: Execute Disable Bit enable. + // CPUID 0x80000001 + // Bit 20: Execute Disable Bit available. // - if (EferMsr.Bits.NXE !=3D 0) { - Enabled =3D TRUE; + if (Edx.Bits.NX !=3D 0) { + EferMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); + // + // MSR 0xC0000080 + // Bit 11: Execute Disable Bit enable. + // + if (EferMsr.Bits.NXE !=3D 0) { + Enabled =3D TRUE; + } } } } -- 2.9.3.windows.2