From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=216.228.121.64; helo=hqemgate15.nvidia.com; envelope-from=jbrasen@nvidia.com; receiver=edk2-devel@lists.01.org Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DB1D6211BB8AD for ; Wed, 30 Jan 2019 15:59:15 -0800 (PST) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 30 Jan 2019 15:58:41 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 30 Jan 2019 15:59:09 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 30 Jan 2019 15:59:09 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 30 Jan 2019 23:59:09 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 30 Jan 2019 23:59:09 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 30 Jan 2019 23:59:09 +0000 Received: from jbrasen-ux.nvidia.com (Not Verified[10.28.48.113]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 30 Jan 2019 15:59:09 -0800 From: Jeff Brasen To: CC: Edgar Handal , Jeff Brasen Date: Wed, 30 Jan 2019 16:58:40 -0700 Message-ID: <7a0d5c95fdeee0e68f54c8a6a0fbe37c85e76774.1548892644.git.jbrasen@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548892721; bh=MU7k7zr4iMIfLryBwDbd4WflUxeENBG7QzvIPyDGqlE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=dbrmKYVbJXNgWJZucFgW5Yic4FCBtN7gHHZCRRNw0wcnyH6A2zqY4Fa0WbmXx7zXp s0rWVcgINNGw65vqEFJLihCEJaLHrL0pMrzp7Ua3uqaZYJlm8S+6POScBeHx7+fr2n Udycq8SxMbuD/bvUrzaUTCFqVYaVZazxghzLtTGu3/9z8eWmLr8LrS0A2/lM8Y97ks Ev2vTnqacQkZx4XFwU+eq/nxMehygcWQzx1Va9pd4ThsIANsyxQpm1JDU5im1jH+SN bQb25ojLdiUt6D9vF9+ryGEbx4FUdgDDQGMWkv1rsZk4PcKjIWT4IAE7K+KI+cbu77 198hIy7eYEPsA== Subject: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Jan 2019 23:59:16 -0000 Content-Type: text/plain From: Edgar Handal Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register accesses from being split up into 8-bit accesses. The SDHCI specification states that the registers shall be accessable in byte, word, and double word accesses. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 25 ++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 5aec8c6..82f4493 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -152,19 +152,36 @@ SdMmcHcRwMmio ( ) { EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL_WIDTH Width; if ((PciIo == NULL) || (Data == NULL)) { return EFI_INVALID_PARAMETER; } - if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) { - return EFI_INVALID_PARAMETER; + switch (Count) { + case 1: + Width = EfiPciIoWidthUint8; + break; + case 2: + Width = EfiPciIoWidthUint16; + Count = 1; + break; + case 4: + Width = EfiPciIoWidthUint32; + Count = 1; + break; + case 8: + Width = EfiPciIoWidthUint32; + Count = 2; + break; + default: + return EFI_INVALID_PARAMETER; } if (Read) { Status = PciIo->Mem.Read ( PciIo, - EfiPciIoWidthUint8, + Width, BarIndex, (UINT64) Offset, Count, @@ -173,7 +190,7 @@ SdMmcHcRwMmio ( } else { Status = PciIo->Mem.Write ( PciIo, - EfiPciIoWidthUint8, + Width, BarIndex, (UINT64) Offset, Count, -- 2.7.4