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From: "Laszlo Ersek" <lersek@redhat.com>
To: devel@edk2.groups.io, cenjiahui@huawei.com
Cc: Jordan Justen <jordan.l.justen@intel.com>,
	Ard Biesheuvel <ard.biesheuvel@arm.com>,
	Rebecca Cran <rebecca@bsdio.com>,
	Peter Grehan <grehan@freebsd.org>,
	Anthony Perard <anthony.perard@citrix.com>,
	Julien Grall <julien@xen.org>, Leif Lindholm <leif@nuviainc.com>,
	Sami Mujawar <sami.mujawar@arm.com>,
	xieyingtai@huawei.com, wu.wubin@huawei.com,
	Yubo Miao <miaoyubo@huawei.com>
Subject: Re: [edk2-devel] [PATCH v3 4/5] ArmVirtPkg: Add support for extra pci roots
Date: Wed, 6 Jan 2021 11:28:27 +0100	[thread overview]
Message-ID: <7a92fb9d-c4cf-8cc5-715b-36b9c0d4a5e1@redhat.com> (raw)
In-Reply-To: <20201222095944.8686-5-cenjiahui@huawei.com>

On 12/22/20 10:59, Jiahui Cen via groups.io wrote:
> Use utility functions in PciHostBridgeUtilityLib and some platform specific
> functions to add support for extra pci roots in ArmVirtPkg.
> 
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3059
> 
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
> Cc: Leif Lindholm <leif@nuviainc.com>
> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
> Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
> ---
>  ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 138 ++++++++++++++------
>  1 file changed, 101 insertions(+), 37 deletions(-)

Skipping this patch now, due to the required restructuring I outlined
under patch v3 3/5.

Thanks
Laszlo

> 
> diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> index d554479bf0de..a29dcecf7044 100644
> --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> @@ -7,6 +7,7 @@
>  
>  **/
>  #include <PiDxe.h>
> +#include <Library/BaseMemoryLib.h>
>  #include <Library/DebugLib.h>
>  #include <Library/DevicePathLib.h>
>  #include <Library/DxeServicesTableLib.h>
> @@ -302,7 +303,60 @@ ProcessPciHost (
>    return Status;
>  }
>  
> -STATIC PCI_ROOT_BRIDGE mRootBridge;
> +EFI_STATUS
> +InitRootBridge (
> +  IN  UINT64                   Supports,
> +  IN  UINT64                   Attributes,
> +  IN  UINT64                   AllocAttributes,
> +  IN  UINT8                    RootBusNumber,
> +  IN  UINT8                    MaxSubBusNumber,
> +  IN  PCI_ROOT_BRIDGE_APERTURE *Io,
> +  IN  PCI_ROOT_BRIDGE_APERTURE *Mem,
> +  IN  PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
> +  IN  PCI_ROOT_BRIDGE_APERTURE *PMem,
> +  IN  PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
> +  OUT PCI_ROOT_BRIDGE          *RootBus
> +  )
> +{
> +  EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
> +
> +  //
> +  // Be safe if other fields are added to PCI_ROOT_BRIDGE later.
> +  //
> +  ZeroMem (RootBus, sizeof *RootBus);
> +
> +  RootBus->Segment = 0;
> +
> +  RootBus->Supports   = Supports;
> +  RootBus->Attributes = Attributes;
> +
> +  RootBus->DmaAbove4G = TRUE;
> +
> +  RootBus->AllocationAttributes = AllocAttributes;
> +  RootBus->Bus.Base  = RootBusNumber;
> +  RootBus->Bus.Limit = MaxSubBusNumber;
> +  CopyMem (&RootBus->Io, Io, sizeof (*Io));
> +  CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));
> +  CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));
> +  CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));
> +  CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));
> +
> +  RootBus->NoExtendedConfigSpace = FALSE;
> +
> +  DevicePath = AllocateCopyPool (sizeof mEfiPciRootBridgeDevicePath,
> +                 &mEfiPciRootBridgeDevicePath);
> +  if (DevicePath == NULL) {
> +    DEBUG ((DEBUG_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
> +    return EFI_OUT_OF_RESOURCES;
> +  }
> +  DevicePath->AcpiDevicePath.UID = RootBusNumber;
> +  RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
> +
> +  DEBUG ((DEBUG_INFO,
> +    "%a: populated root bus %d, with room for %d subordinate bus(es)\n",
> +    __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
> +  return EFI_SUCCESS;
> +}
>  
>  /**
>    Return all the root bridge instances in an array.
> @@ -319,11 +373,18 @@ PciHostBridgeGetRootBridges (
>    UINTN *Count
>    )
>  {
> -  UINT64              IoBase, IoSize;
> -  UINT64              Mmio32Base, Mmio32Size;
> -  UINT64              Mmio64Base, Mmio64Size;
> -  UINT32              BusMin, BusMax;
> -  EFI_STATUS          Status;
> +  UINT64                   IoBase, IoSize;
> +  UINT64                   Mmio32Base, Mmio32Size;
> +  UINT64                   Mmio64Base, Mmio64Size;
> +  UINT32                   BusMin, BusMax;
> +  EFI_STATUS               Status;
> +  UINT64                   Attributes;
> +  UINT64                   AllocationAttributes;
> +  PCI_ROOT_BRIDGE_APERTURE Io;
> +  PCI_ROOT_BRIDGE_APERTURE Mem;
> +  PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
> +  PCI_ROOT_BRIDGE_APERTURE PMem;
> +  PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
>  
>    if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
>      DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
> @@ -341,33 +402,27 @@ PciHostBridgeGetRootBridges (
>      return NULL;
>    }
>  
> -  *Count = 1;
> +  ZeroMem (&Io, sizeof (Io));
> +  ZeroMem (&Mem, sizeof (Mem));
> +  ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
>  
> -  mRootBridge.Segment               = 0;
> -  mRootBridge.Supports              = EFI_PCI_ATTRIBUTE_ISA_IO_16 |
> -                                      EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
> -                                      EFI_PCI_ATTRIBUTE_VGA_IO_16  |
> -                                      EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
> -  mRootBridge.Attributes            = mRootBridge.Supports;
> +  Attributes = EFI_PCI_ATTRIBUTE_ISA_IO_16 |
> +               EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
> +               EFI_PCI_ATTRIBUTE_VGA_IO_16  |
> +               EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
>  
> -  mRootBridge.DmaAbove4G            = TRUE;
> -  mRootBridge.NoExtendedConfigSpace = FALSE;
> -  mRootBridge.ResourceAssigned      = FALSE;
> +  AllocationAttributes  = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
>  
> -  mRootBridge.AllocationAttributes  = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
> -
> -  mRootBridge.Bus.Base              = BusMin;
> -  mRootBridge.Bus.Limit             = BusMax;
> -  mRootBridge.Io.Base               = IoBase;
> -  mRootBridge.Io.Limit              = IoBase + IoSize - 1;
> -  mRootBridge.Mem.Base              = Mmio32Base;
> -  mRootBridge.Mem.Limit             = Mmio32Base + Mmio32Size - 1;
> +  Io.Base               = IoBase;
> +  Io.Limit              = IoBase + IoSize - 1;
> +  Mem.Base              = Mmio32Base;
> +  Mem.Limit             = Mmio32Base + Mmio32Size - 1;
>  
>    if (sizeof (UINTN) == sizeof (UINT64)) {
> -    mRootBridge.MemAbove4G.Base       = Mmio64Base;
> -    mRootBridge.MemAbove4G.Limit      = Mmio64Base + Mmio64Size - 1;
> +    MemAbove4G.Base       = Mmio64Base;
> +    MemAbove4G.Limit      = Mmio64Base + Mmio64Size - 1;
>      if (Mmio64Size > 0) {
> -      mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
> +      AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
>      }
>    } else {
>      //
> @@ -376,21 +431,30 @@ PciHostBridgeGetRootBridges (
>      // BARs unless they are allocated below 4 GB. So ignore the range above
>      // 4 GB in this case.
>      //
> -    mRootBridge.MemAbove4G.Base       = MAX_UINT64;
> -    mRootBridge.MemAbove4G.Limit      = 0;
> +    MemAbove4G.Base       = MAX_UINT64;
> +    MemAbove4G.Limit      = 0;
>    }
>  
>    //
>    // No separate ranges for prefetchable and non-prefetchable BARs
>    //
> -  mRootBridge.PMem.Base             = MAX_UINT64;
> -  mRootBridge.PMem.Limit            = 0;
> -  mRootBridge.PMemAbove4G.Base      = MAX_UINT64;
> -  mRootBridge.PMemAbove4G.Limit     = 0;
> +  PMem.Base             = MAX_UINT64;
> +  PMem.Limit            = 0;
> +  PMemAbove4G.Base      = MAX_UINT64;
> +  PMemAbove4G.Limit     = 0;
>  
> -  mRootBridge.DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
> -
> -  return &mRootBridge;
> +  return PciHostBridgeUtilityExtraRoots (
> +    Count,
> +    BusMin,
> +    BusMax,
> +    Attributes,
> +    AllocationAttributes,
> +    Io,
> +    Mem,
> +    MemAbove4G,
> +    PMem,
> +    PMemAbove4G
> +  );
>  }
>  
>  /**
> @@ -407,7 +471,7 @@ PciHostBridgeFreeRootBridges (
>    UINTN           Count
>    )
>  {
> -  ASSERT (Count == 1);
> +  PciHostBridgeUtilityFreeRootBridges (Bridges, Count);
>  }
>  
>  /**
> 


  reply	other threads:[~2021-01-06 10:28 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-22  9:59 [PATCH v3 0/5] Add extra pci roots support for Arm Jiahui Cen
2020-12-22  9:59 ` [PATCH v3 1/5] OvmfPkg: Introduce PciHostBridgeUtilityLib class Jiahui Cen
2021-01-06  8:51   ` [edk2-devel] " Laszlo Ersek
2021-01-07  5:44     ` Jiahui Cen
2020-12-22  9:59 ` [PATCH v3 2/5] ArmVirtPkg: Refactor with PciHostBridgeUtilityLib Jiahui Cen
2021-01-06  9:12   ` [edk2-devel] " Laszlo Ersek
2021-01-07  5:44     ` Jiahui Cen
2020-12-22  9:59 ` [PATCH v3 3/5] OvmfPkg: Extract functions for extra pci roots Jiahui Cen
2021-01-06 10:27   ` [edk2-devel] " Laszlo Ersek
2021-01-07  5:47     ` Jiahui Cen
2020-12-22  9:59 ` [PATCH v3 4/5] ArmVirtPkg: Add support " Jiahui Cen
2021-01-06 10:28   ` Laszlo Ersek [this message]
2020-12-22  9:59 ` [PATCH v3 5/5] ArmVirtPkg/ArmVirtQemu: Add support for HotPlug Jiahui Cen
2021-01-06 10:31   ` [edk2-devel] " Laszlo Ersek
2021-01-07  5:47     ` Jiahui Cen

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