From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.groups.io with SMTP id smtpd.web11.6168.1609928918104742814 for ; Wed, 06 Jan 2021 02:28:38 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=ihRzZDmw; spf=pass (domain: redhat.com, ip: 216.205.24.124, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1609928917; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QKjv2s/oSFBoXDSPraEa97qLmyS1VDaSBV3ovlLuwx8=; b=ihRzZDmwBY+q1ZCCDQ1Kz4RdwMjizLcWD0/4rsTXhTjx3etPVYIoSIp+VEl5FlSgClRGOx TmdGnV+FRw1mERPI3qHLA8zyJaaulPHCLuxT7aKhFqepRHpoU2IdlHYCVX5Q3qgr7Vr9fW /2Es3+PnzHOHtc7DSisTJ52dKLk6LCY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-405-eWK6BoGjNNiV9_Fz5fupKg-1; Wed, 06 Jan 2021 05:28:33 -0500 X-MC-Unique: eWK6BoGjNNiV9_Fz5fupKg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5194C800D62; Wed, 6 Jan 2021 10:28:31 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-112-192.ams2.redhat.com [10.36.112.192]) by smtp.corp.redhat.com (Postfix) with ESMTP id 46D8A7046D; Wed, 6 Jan 2021 10:28:28 +0000 (UTC) Subject: Re: [edk2-devel] [PATCH v3 4/5] ArmVirtPkg: Add support for extra pci roots To: devel@edk2.groups.io, cenjiahui@huawei.com Cc: Jordan Justen , Ard Biesheuvel , Rebecca Cran , Peter Grehan , Anthony Perard , Julien Grall , Leif Lindholm , Sami Mujawar , xieyingtai@huawei.com, wu.wubin@huawei.com, Yubo Miao References: <20201222095944.8686-1-cenjiahui@huawei.com> <20201222095944.8686-5-cenjiahui@huawei.com> From: "Laszlo Ersek" Message-ID: <7a92fb9d-c4cf-8cc5-715b-36b9c0d4a5e1@redhat.com> Date: Wed, 6 Jan 2021 11:28:27 +0100 MIME-Version: 1.0 In-Reply-To: <20201222095944.8686-5-cenjiahui@huawei.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=lersek@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 12/22/20 10:59, Jiahui Cen via groups.io wrote: > Use utility functions in PciHostBridgeUtilityLib and some platform specific > functions to add support for extra pci roots in ArmVirtPkg. > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3059 > > Cc: Laszlo Ersek > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Signed-off-by: Jiahui Cen > Signed-off-by: Yubo Miao > --- > ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 138 ++++++++++++++------ > 1 file changed, 101 insertions(+), 37 deletions(-) Skipping this patch now, due to the required restructuring I outlined under patch v3 3/5. Thanks Laszlo > > diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c > index d554479bf0de..a29dcecf7044 100644 > --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c > +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c > @@ -7,6 +7,7 @@ > > **/ > #include > +#include > #include > #include > #include > @@ -302,7 +303,60 @@ ProcessPciHost ( > return Status; > } > > -STATIC PCI_ROOT_BRIDGE mRootBridge; > +EFI_STATUS > +InitRootBridge ( > + IN UINT64 Supports, > + IN UINT64 Attributes, > + IN UINT64 AllocAttributes, > + IN UINT8 RootBusNumber, > + IN UINT8 MaxSubBusNumber, > + IN PCI_ROOT_BRIDGE_APERTURE *Io, > + IN PCI_ROOT_BRIDGE_APERTURE *Mem, > + IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, > + IN PCI_ROOT_BRIDGE_APERTURE *PMem, > + IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G, > + OUT PCI_ROOT_BRIDGE *RootBus > + ) > +{ > + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; > + > + // > + // Be safe if other fields are added to PCI_ROOT_BRIDGE later. > + // > + ZeroMem (RootBus, sizeof *RootBus); > + > + RootBus->Segment = 0; > + > + RootBus->Supports = Supports; > + RootBus->Attributes = Attributes; > + > + RootBus->DmaAbove4G = TRUE; > + > + RootBus->AllocationAttributes = AllocAttributes; > + RootBus->Bus.Base = RootBusNumber; > + RootBus->Bus.Limit = MaxSubBusNumber; > + CopyMem (&RootBus->Io, Io, sizeof (*Io)); > + CopyMem (&RootBus->Mem, Mem, sizeof (*Mem)); > + CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G)); > + CopyMem (&RootBus->PMem, PMem, sizeof (*PMem)); > + CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G)); > + > + RootBus->NoExtendedConfigSpace = FALSE; > + > + DevicePath = AllocateCopyPool (sizeof mEfiPciRootBridgeDevicePath, > + &mEfiPciRootBridgeDevicePath); > + if (DevicePath == NULL) { > + DEBUG ((DEBUG_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES)); > + return EFI_OUT_OF_RESOURCES; > + } > + DevicePath->AcpiDevicePath.UID = RootBusNumber; > + RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath; > + > + DEBUG ((DEBUG_INFO, > + "%a: populated root bus %d, with room for %d subordinate bus(es)\n", > + __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber)); > + return EFI_SUCCESS; > +} > > /** > Return all the root bridge instances in an array. > @@ -319,11 +373,18 @@ PciHostBridgeGetRootBridges ( > UINTN *Count > ) > { > - UINT64 IoBase, IoSize; > - UINT64 Mmio32Base, Mmio32Size; > - UINT64 Mmio64Base, Mmio64Size; > - UINT32 BusMin, BusMax; > - EFI_STATUS Status; > + UINT64 IoBase, IoSize; > + UINT64 Mmio32Base, Mmio32Size; > + UINT64 Mmio64Base, Mmio64Size; > + UINT32 BusMin, BusMax; > + EFI_STATUS Status; > + UINT64 Attributes; > + UINT64 AllocationAttributes; > + PCI_ROOT_BRIDGE_APERTURE Io; > + PCI_ROOT_BRIDGE_APERTURE Mem; > + PCI_ROOT_BRIDGE_APERTURE MemAbove4G; > + PCI_ROOT_BRIDGE_APERTURE PMem; > + PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; > > if (PcdGet64 (PcdPciExpressBaseAddress) == 0) { > DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__)); > @@ -341,33 +402,27 @@ PciHostBridgeGetRootBridges ( > return NULL; > } > > - *Count = 1; > + ZeroMem (&Io, sizeof (Io)); > + ZeroMem (&Mem, sizeof (Mem)); > + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); > > - mRootBridge.Segment = 0; > - mRootBridge.Supports = EFI_PCI_ATTRIBUTE_ISA_IO_16 | > - EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | > - EFI_PCI_ATTRIBUTE_VGA_IO_16 | > - EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; > - mRootBridge.Attributes = mRootBridge.Supports; > + Attributes = EFI_PCI_ATTRIBUTE_ISA_IO_16 | > + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | > + EFI_PCI_ATTRIBUTE_VGA_IO_16 | > + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; > > - mRootBridge.DmaAbove4G = TRUE; > - mRootBridge.NoExtendedConfigSpace = FALSE; > - mRootBridge.ResourceAssigned = FALSE; > + AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM; > > - mRootBridge.AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM; > - > - mRootBridge.Bus.Base = BusMin; > - mRootBridge.Bus.Limit = BusMax; > - mRootBridge.Io.Base = IoBase; > - mRootBridge.Io.Limit = IoBase + IoSize - 1; > - mRootBridge.Mem.Base = Mmio32Base; > - mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1; > + Io.Base = IoBase; > + Io.Limit = IoBase + IoSize - 1; > + Mem.Base = Mmio32Base; > + Mem.Limit = Mmio32Base + Mmio32Size - 1; > > if (sizeof (UINTN) == sizeof (UINT64)) { > - mRootBridge.MemAbove4G.Base = Mmio64Base; > - mRootBridge.MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1; > + MemAbove4G.Base = Mmio64Base; > + MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1; > if (Mmio64Size > 0) { > - mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; > + AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; > } > } else { > // > @@ -376,21 +431,30 @@ PciHostBridgeGetRootBridges ( > // BARs unless they are allocated below 4 GB. So ignore the range above > // 4 GB in this case. > // > - mRootBridge.MemAbove4G.Base = MAX_UINT64; > - mRootBridge.MemAbove4G.Limit = 0; > + MemAbove4G.Base = MAX_UINT64; > + MemAbove4G.Limit = 0; > } > > // > // No separate ranges for prefetchable and non-prefetchable BARs > // > - mRootBridge.PMem.Base = MAX_UINT64; > - mRootBridge.PMem.Limit = 0; > - mRootBridge.PMemAbove4G.Base = MAX_UINT64; > - mRootBridge.PMemAbove4G.Limit = 0; > + PMem.Base = MAX_UINT64; > + PMem.Limit = 0; > + PMemAbove4G.Base = MAX_UINT64; > + PMemAbove4G.Limit = 0; > > - mRootBridge.DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath; > - > - return &mRootBridge; > + return PciHostBridgeUtilityExtraRoots ( > + Count, > + BusMin, > + BusMax, > + Attributes, > + AllocationAttributes, > + Io, > + Mem, > + MemAbove4G, > + PMem, > + PMemAbove4G > + ); > } > > /** > @@ -407,7 +471,7 @@ PciHostBridgeFreeRootBridges ( > UINTN Count > ) > { > - ASSERT (Count == 1); > + PciHostBridgeUtilityFreeRootBridges (Bridges, Count); > } > > /** >