From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web08.4332.1664231720280448342 for ; Mon, 26 Sep 2022 15:35:20 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=NyGn839Y; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28QMIbPe023769; Mon, 26 Sep 2022 22:35:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=jMyuqf5Ael8NOUlQlZlQL1+V0hmvcnkPwch+4wGkRu0=; b=NyGn839Y/Eiw0gN3SZe9YxPjIvo2Z0C16ROoHACOZAOILJeZtt6YKiEX8jhfRp4oxSpK jf0rd6Kcm9/yMyHLErJtH9YCYp9SaOmL2PMA9reU7tFqSYvA+6uj6igbLCeEl7VtEbTE CQyUrpw7LuKlafxemWlvOqEIi2gONya3BlAaLyDBIFVV+e52lQsC24AooV/g/z/HMTEh u0IW8mdfAbxT8mQk6KKps48a8zWY0EZE/aDYovJszXv/5+jKL5o8grpmDTtu+1AOxc0F zVV2PkxnkyAmAdFuEAWGVzvEJh2TfntshW8L2oUu+WXGczaeVswzmpkzPw142+iel3of 1g== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jssg6vs42-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 26 Sep 2022 22:35:17 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28QMZGFC007394 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 26 Sep 2022 22:35:16 GMT Received: from [10.110.26.2] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 26 Sep 2022 15:35:16 -0700 Message-ID: <7d5a2a72-3aed-9aa8-f5cc-edb7635a7d4e@quicinc.com> Date: Mon, 26 Sep 2022 15:35:15 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v3 07/16] ArmPkg/ArmMmuLib: permit initial configuration with MMU enabled To: Ard Biesheuvel , CC: Alexander Graf References: <20220926082511.2110797-1-ardb@kernel.org> <20220926082511.2110797-8-ardb@kernel.org> From: "Leif Lindholm" In-Reply-To: <20220926082511.2110797-8-ardb@kernel.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: n1aFb7d64nxBpNztAIbYNdzFO67BimMB X-Proofpoint-ORIG-GUID: n1aFb7d64nxBpNztAIbYNdzFO67BimMB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-26_11,2022-09-22_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 phishscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 malwarescore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209260139 Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 2022-09-26 01:25, Ard Biesheuvel wrote: > Permit the use of this library with the MMU and caches already enabled. > This removes the need for any cache maintenance for coherency, and is > generally better for robustness and performance, especially when running > under virtualization. > > Note that this means we have to defer assignment of TTBR0 until the > page tables are ready to be used, and so UpdateRegionMapping() can no > longer read back TTBR0 directly to discover the root table address. > > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm / Leif > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 48 +++++++++++--------- > 1 file changed, 26 insertions(+), 22 deletions(-) > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index 4d75788ed2b2..ae59e9a7d04e 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -357,6 +357,7 @@ UpdateRegionMapping ( > IN UINT64 RegionLength, > > IN UINT64 AttributeSetMask, > > IN UINT64 AttributeClearMask, > > + IN UINT64 *RootTable, > > IN BOOLEAN TableIsLive > > ) > > { > > @@ -373,7 +374,7 @@ UpdateRegionMapping ( > RegionStart + RegionLength, > > AttributeSetMask, > > AttributeClearMask, > > - ArmGetTTBR0BaseAddress (), > > + RootTable, > > GetRootTableLevel (T0SZ), > > TableIsLive > > ); > > @@ -391,6 +392,7 @@ FillTranslationTable ( > MemoryRegion->Length, > > ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF, > > 0, > > + RootTable, > > FALSE > > ); > > } > > @@ -466,6 +468,7 @@ ArmSetMemoryAttributes ( > Length, > > PageAttributes, > > PageAttributeMask, > > + ArmGetTTBR0BaseAddress (), > > TRUE > > ); > > } > > @@ -484,6 +487,7 @@ SetMemoryRegionAttribute ( > Length, > > Attributes, > > BlockEntryMask, > > + ArmGetTTBR0BaseAddress (), > > TRUE > > ); > > } > > @@ -675,14 +679,6 @@ ArmConfigureMmu ( > return EFI_OUT_OF_RESOURCES; > > } > > > > - // > > - // We set TTBR0 just after allocating the table to retrieve its location from > > - // the subsequent functions without needing to pass this value across the > > - // functions. The MMU is only enabled after the translation tables are > > - // populated. > > - // > > - ArmSetTTBR0 (TranslationTable); > > - > > if (TranslationTableBase != NULL) { > > *TranslationTableBase = TranslationTable; > > } > > @@ -691,14 +687,17 @@ ArmConfigureMmu ( > *TranslationTableSize = RootTableEntryCount * sizeof (UINT64); > > } > > > > - // > > - // Make sure we are not inadvertently hitting in the caches > > - // when populating the page tables. > > - // > > - InvalidateDataCacheRange ( > > - TranslationTable, > > - RootTableEntryCount * sizeof (UINT64) > > - ); > > + if (!ArmMmuEnabled ()) { > > + // > > + // Make sure we are not inadvertently hitting in the caches > > + // when populating the page tables. > > + // > > + InvalidateDataCacheRange ( > > + TranslationTable, > > + RootTableEntryCount * sizeof (UINT64) > > + ); > > + } > > + > > ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64)); > > > > while (MemoryTable->Length != 0) { > > @@ -723,12 +722,17 @@ ArmConfigureMmu ( > MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK) > > ); > > > > - ArmDisableAlignmentCheck (); > > - ArmEnableStackAlignmentCheck (); > > - ArmEnableInstructionCache (); > > - ArmEnableDataCache (); > > + ArmSetTTBR0 (TranslationTable); > > + > > + if (!ArmMmuEnabled ()) { > > + ArmDisableAlignmentCheck (); > > + ArmEnableStackAlignmentCheck (); > > + ArmEnableInstructionCache (); > > + ArmEnableDataCache (); > > + > > + ArmEnableMmu (); > > + } > > > > - ArmEnableMmu (); > > return EFI_SUCCESS; > > > > FreeTranslationTable: >