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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4041.namprd12.prod.outlook.com (2603:10b6:5:210::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.15; Mon, 2 Mar 2020 23:07:42 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:41 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v5 13/42] UefiCpuPkg/CpuExceptionHandler: Add support for CPUID NAE events Date: Mon, 2 Mar 2020 17:06:44 -0600 Message-Id: <7ddc1fb041070f3e5dc001f5a89514034a4bfd39.1583190432.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: 45gPSor06NJ7wfzgfIPXmJUAT7HV9MCl6IW+dbB6Pa6bU0vNAJpnWPWRe4D3t6iYdZkv0ELSWcnFul73+2qkqA5TtABYn+Skb4jc48f4patwPIz7ew8xeXAJD4vTIxcptGLu5AsnfYl8wllkJYab1bGvhdsi/mJE/mkRRPndP4IcGsefCzIwzPiUdnQEXlsTU5qVaWUB7FL0tkrs2uQRWQvQZbK0/rdt9cL28NPx2RuT8/1HWNiGkjPxnPCYkGjIqTKADmJ93xD4ZYFnVH9QRnk9/2NzFWE78PKrRRrxK6c+DklQqhW/1rD97r+jfqY098oC6uwBEKWitBpV4Upt3evHGoU72ESIe397jsnIbvCZWBpE+mJKPdj7kCCLnOenlY4EGY5AXv0HXOcUklNBHVB63MNSrAO38sm2b6e/mnJ53t2fChDIk9pFL8kVFOUp5J7M5Azp6kKwivV+pDPkWEc6UXh+XQ/fRI1SSGU5xt48Zq7iz77TRKAhKUSY3IFDJoZd32qZv470BcxHW2aGBA== X-MS-Exchange-AntiSpam-MessageData: S3bxwi7weB5WL7l+HDlri/xdcqZg0y1524UuDvShwkFerdx/yjXTy+qWhSL+efd4f3u8p1YUL8Hs/EkbvmLN6bG4CUc45mbDsABpovcbhUXETneH4pQtCCBSZcnHOLsZlyAWpfJT6FRSFzHY8Vqrvg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5efb061a-f71d-4142-0ab3-08d7befe826e X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:41.8753 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EalA+7IkXMon59rmptTaSObRmgqItcvrXt5EN8B1+KmwDXBq7v1r1mchXlyMtz+gWxoXS5jVfzt/Mxhy+RK2HA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a CPUID NAE event. Additionally, CPUID 0x0000_000d requires XCR0 to be supplied in the GHCB, so add support to issue the XGETBV instruction. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 28adf0d5e9c4..970ee8752253 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -11,6 +11,8 @@ #include #include "AMDSevVcCommon.h" +#define CR4_OSXSAVE (1 << 18) + typedef enum { LongMode64Bit = 0, LongModeCompat32Bit, @@ -494,6 +496,44 @@ IoioExit ( return 0; } +STATIC +UINT64 +CpuidExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Ghcb->SaveArea.Rax = Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx = Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + if (Regs->Rax == 0x0000000d) { + Ghcb->SaveArea.XCr0 = (AsmReadCr4 () & CR4_OSXSAVE) ? AsmXGetBv (0) : 1; + GhcbSetRegValid (Ghcb, GhcbXCr0); + } + + Status = VmgExit (Ghcb, SvmExitCpuid, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRbx) || + !GhcbIsRegValid (Ghcb, GhcbRcx) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax = Ghcb->SaveArea.Rax; + Regs->Rbx = Ghcb->SaveArea.Rbx; + Regs->Rcx = Ghcb->SaveArea.Rcx; + Regs->Rdx = Ghcb->SaveArea.Rdx; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -510,6 +550,10 @@ DoVcCommon ( ExitCode = Regs->ExceptionData; switch (ExitCode) { + case SvmExitCpuid: + NaeExit = CpuidExit; + break; + case SvmExitIoioProt: NaeExit = IoioExit; break; -- 2.17.1