From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: philmd@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Tue, 24 Sep 2019 04:44:16 -0700 Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CCD21369CA for ; Tue, 24 Sep 2019 11:44:15 +0000 (UTC) Received: by mail-wr1-f72.google.com with SMTP id t11so464009wrq.19 for ; Tue, 24 Sep 2019 04:44:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=jK4BWeLMP/6PAtDSIVY7K4dxlMakQ76gpQgipV/X2Vg=; b=JqfUmCoZp/Rppv7HLnCmgNhUEoMsZI5ALgYSBtVxyv/A560bVODUf29LyjnejPG16I 7COGFhjOdVONn7fbHXQ0E6IXjW32tXh7nVpw04pBsfL4/jNCVORY8Mmecbo/MJxM9f5J 2lagHcM2ZUQ/J09+HdCV7qvI3sqkXUVVZX5k+MgNBb9hg5xDtMiJTLplFSWh8T/58KEY o0pWNl5jd9uLuWTOMgyRKdzszyuYg+sFeN5DSQqN3JERTOs9MfXzsfdeVryHbjOYRGh0 8EO97JtSPOfGBuGCU2AJ+uTOqGsA4HhVIpzAzknSdQnebNMinG1dgJfPsv6QL3X+NMb3 iDnQ== X-Gm-Message-State: APjAAAX1zlutM/X6UsNZ5EthkF6fT03BliOb8o8XBeQ5Kp5s3srA6UsP nnC+KDfWUIlXquITgpyAIJ3rKm74fW9mgw2FbM7PYLElNgi+uGRvHLtMxyd+nsHsJMX4RdLgIpy 9vmmI+AxCPHs6fw== X-Received: by 2002:a5d:6a90:: with SMTP id s16mr1943933wru.284.1569325454573; Tue, 24 Sep 2019 04:44:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqwaT5Bss3masA+fg+/NhxPaY45VfuIX5LrvF1/5C1KBgUOBceeRO8SbT6SKaDfVhtk/lsRwzQ== X-Received: by 2002:a5d:6a90:: with SMTP id s16mr1943916wru.284.1569325454379; Tue, 24 Sep 2019 04:44:14 -0700 (PDT) Received: from [192.168.1.115] (240.red-88-21-68.staticip.rima-tde.net. [88.21.68.240]) by smtp.gmail.com with ESMTPSA id u68sm2766435wmu.12.2019.09.24.04.44.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Sep 2019 04:44:13 -0700 (PDT) Subject: Re: [edk2-devel] [PATCH wave 1 02/10] OvmfPkg/IndustryStandard: increase vertical whitespace in Q35 macro defs To: devel@edk2.groups.io, lersek@redhat.com Cc: Ard Biesheuvel , Boris Ostrovsky , Brijesh Singh , Igor Mammedov , Jiewen Yao , Joao M Martins , Jordan Justen , Jun Nakajima , Michael Kinney , Paolo Bonzini , Phillip Goerl , Yingwen Chen References: <20190924113505.27272-1-lersek@redhat.com> <20190924113505.27272-3-lersek@redhat.com> From: =?UTF-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <7f131697-c25f-cc2d-ca0e-9327f6086823@redhat.com> Date: Tue, 24 Sep 2019 13:44:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190924113505.27272-3-lersek@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 9/24/19 1:34 PM, Laszlo Ersek wrote: > In a subsequent patch, we'll introduce new DRAM controller macros in > "Q35MchIch9.h". Their names are too long for the currently available > vertical whitespace, so increase the latter first. > > There is no functional change in this patch ("git show -b" displays > nothing). > > Cc: Ard Biesheuvel > Cc: Boris Ostrovsky > Cc: Brijesh Singh > Cc: Igor Mammedov > Cc: Jiewen Yao > Cc: Joao M Martins > Cc: Jordan Justen > Cc: Jun Nakajima > Cc: Michael Kinney > Cc: Paolo Bonzini > Cc: Phillip Goerl > Cc: Yingwen Chen > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1512 > Signed-off-by: Laszlo Ersek > --- > OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 100 ++++++++++---------- > 1 file changed, 50 insertions(+), 50 deletions(-) > > diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > index 391cb4622226..614699ab38f1 100644 > --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > @@ -27,56 +27,56 @@ > // > #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) > > -#define MCH_EXT_TSEG_MB 0x50 > -#define MCH_EXT_TSEG_MB_QUERY 0xFFFF > - > -#define MCH_GGC 0x52 > -#define MCH_GGC_IVD BIT1 > - > -#define MCH_PCIEXBAR_LOW 0x60 > -#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF > -#define MCH_PCIEXBAR_BUS_FF 0 > -#define MCH_PCIEXBAR_EN BIT0 > - > -#define MCH_PCIEXBAR_HIGH 0x64 > -#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0 > - > -#define MCH_PAM0 0x90 > -#define MCH_PAM1 0x91 > -#define MCH_PAM2 0x92 > -#define MCH_PAM3 0x93 > -#define MCH_PAM4 0x94 > -#define MCH_PAM5 0x95 > -#define MCH_PAM6 0x96 > - > -#define MCH_SMRAM 0x9D > -#define MCH_SMRAM_D_LCK BIT4 > -#define MCH_SMRAM_G_SMRAME BIT3 > - > -#define MCH_ESMRAMC 0x9E > -#define MCH_ESMRAMC_H_SMRAME BIT7 > -#define MCH_ESMRAMC_E_SMERR BIT6 > -#define MCH_ESMRAMC_SM_CACHE BIT5 > -#define MCH_ESMRAMC_SM_L1 BIT4 > -#define MCH_ESMRAMC_SM_L2 BIT3 > -#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1) > -#define MCH_ESMRAMC_TSEG_8MB BIT2 > -#define MCH_ESMRAMC_TSEG_2MB BIT1 > -#define MCH_ESMRAMC_TSEG_1MB 0 > -#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) > -#define MCH_ESMRAMC_T_EN BIT0 > - > -#define MCH_GBSM 0xA4 > -#define MCH_GBSM_MB_SHIFT 20 > - > -#define MCH_BGSM 0xA8 > -#define MCH_BGSM_MB_SHIFT 20 > - > -#define MCH_TSEGMB 0xAC > -#define MCH_TSEGMB_MB_SHIFT 20 > - > -#define MCH_TOLUD 0xB0 > -#define MCH_TOLUD_MB_SHIFT 4 > +#define MCH_EXT_TSEG_MB 0x50 > +#define MCH_EXT_TSEG_MB_QUERY 0xFFFF > + > +#define MCH_GGC 0x52 > +#define MCH_GGC_IVD BIT1 > + > +#define MCH_PCIEXBAR_LOW 0x60 > +#define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF > +#define MCH_PCIEXBAR_BUS_FF 0 > +#define MCH_PCIEXBAR_EN BIT0 > + > +#define MCH_PCIEXBAR_HIGH 0x64 > +#define MCH_PCIEXBAR_HIGHMASK 0xFFFFFFF0 > + > +#define MCH_PAM0 0x90 > +#define MCH_PAM1 0x91 > +#define MCH_PAM2 0x92 > +#define MCH_PAM3 0x93 > +#define MCH_PAM4 0x94 > +#define MCH_PAM5 0x95 > +#define MCH_PAM6 0x96 > + > +#define MCH_SMRAM 0x9D > +#define MCH_SMRAM_D_LCK BIT4 > +#define MCH_SMRAM_G_SMRAME BIT3 > + > +#define MCH_ESMRAMC 0x9E > +#define MCH_ESMRAMC_H_SMRAME BIT7 > +#define MCH_ESMRAMC_E_SMERR BIT6 > +#define MCH_ESMRAMC_SM_CACHE BIT5 > +#define MCH_ESMRAMC_SM_L1 BIT4 > +#define MCH_ESMRAMC_SM_L2 BIT3 > +#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1) > +#define MCH_ESMRAMC_TSEG_8MB BIT2 > +#define MCH_ESMRAMC_TSEG_2MB BIT1 > +#define MCH_ESMRAMC_TSEG_1MB 0 > +#define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) > +#define MCH_ESMRAMC_T_EN BIT0 > + > +#define MCH_GBSM 0xA4 > +#define MCH_GBSM_MB_SHIFT 20 > + > +#define MCH_BGSM 0xA8 > +#define MCH_BGSM_MB_SHIFT 20 > + > +#define MCH_TSEGMB 0xAC > +#define MCH_TSEGMB_MB_SHIFT 20 > + > +#define MCH_TOLUD 0xB0 > +#define MCH_TOLUD_MB_SHIFT 4 > > // > // B/D/F/Type: 0/0x1f/0/PCI > Reviewed-by: Philippe Mathieu-Daude Tested-by: Philippe Mathieu-Daude