From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.77677.1675750527236321687 for ; Mon, 06 Feb 2023 22:15:27 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: vivek.gautam@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 352BA1063; Mon, 6 Feb 2023 22:16:09 -0800 (PST) Received: from [10.162.40.135] (a077843.arm.com [10.162.40.135]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 590413F8C6; Mon, 6 Feb 2023 22:15:24 -0800 (PST) Message-ID: <8086be9f-20e7-f77c-ac73-d378540dfd9f@arm.com> Date: Tue, 7 Feb 2023 11:45:22 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [edk2-platforms][PATCH V2 0/5] Enable SoC expansion block and Virtio-P9 for RD-N2 variants To: Pierre Gondois , devel@edk2.groups.io Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, Sami.Mujawar@arm.com References: <20230127092338.72056-1-vivek.gautam@arm.com> From: "Vivek Kumar Gautam" In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Hi Pierre, On 2/3/23 21:28, Pierre Gondois wrote: > Hello Vivek, >=20 > On 1/27/23 10:23, Vivek Gautam wrote: >> Arm reference design Fixed Virtual Platforms (FVPs) such as the RD-N2 >> platform variants have multiple IO virtualization blocks that allow >> connecting PCIe root bus or non-PCIe SoC peripherals to the system. >> Each of these IO virtualization blocks consists of an Arm SMMUv3, a >> GIC-ITS and a NCI (network chip interconnect). >> >> SoC expansion blocks connect to the IO virtualization blocks via x4, x= 8 >> or x16 ports exposed by the system. A SoC expansion block implementati= on >> includes 2 UARTs, 2 DMA devices and 2 Memory nodes. >> >> In addition, Arm reference design platforms support Virtio-P9 device a= s >> part of the Rest of System (RoS). The Virtio-P9 device implements a >> subset of the Plan 9 file protocol over a virtio transport that enable= s >> accessing a shared directory on the host's filesystem from a running >> FVP platform. >> >> This patch series adds SSDT tables for various RD-N2 platforms such as >> RD-N2, RD-N2-Cfg1, and RD-N2-Cfg2 to describe the SoC expansion block >> devices - UARTs, and DMAs and the Virtio-P9 devices present on the >> platforms. The patches also add support for platform DXE driver to >> initialize the UARTs that are present in SoC expansion blocks. By >> default these UARTs are kept disabled and can be enabled with a Pcd - >> PcdIoVirtSocExpBlkUartEnable. >> >> This patch series is now a combination of two patch series [1] and [2] >> that added Virtio-P9 support and SoC expansion block (non-discoverable= ) >> IO block for RD-N2: >> [edk2-platforms][PATCH V1 0/2] Enable Virtio-P9 on RD-N2 platforms >> [edk2-platforms][PATCH V1 0/6] Add non-discoverable IO block for Rd-N2 >> >> [1] https://edk2.groups.io/g/devel/message/94936 >> [2] https://edk2.groups.io/g/devel/message/86646 >> >> Changes since v1: >> =C2=A0 - Minor update to Virtio-P9 SSDT table: >> =C2=A0=C2=A0=C2=A0 - Name of the DefinitionBlock() is set to SsdtRosVi= rtioP9.aml rather >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 than SsdtRosVirtioP9Table.aml >> =C2=A0 - Updates to SoC expansion block: >> =C2=A0=C2=A0=C2=A0 - Removed IORT table for SoC expansion block and ke= pt only the SSDT >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 table for devices. >=20 > Is it possible to know why the IORT table was removed ? The IORT table is removed as that will come along with the common IORT=20 table changes that includes all the GIT ITS nodes, SMMUv3 nodes, PCIe=20 RCs, and the Named Component nodes for DMA PL330 devices. I will update this in the cover letter. >=20 >> =C2=A0=C2=A0=C2=A0 - SSDT table now uses arithmetic operations to calc= ulate the start >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 and end addresses of the devices in QWo= rdMemory() blocks. >> =C2=A0=C2=A0=C2=A0 - The number of PCDs for UARTs and DMAs are now red= uced as the >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addresses are now calculated within the= SSDT table based on the >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 SoC expansion block base address and de= vice offsets. >> =C2=A0=C2=A0=C2=A0 - Defined macros for Interrupt() block for various = DMA nodes. >> =C2=A0=C2=A0=C2=A0 - Removed the first patch of the series that added = PCDs for SMMU: >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 [PATCH V1 1/6] Platform/Sgi: add PCDs f= or SMMUv3 base address=20 >> and interrupts >> =C2=A0=C2=A0=C2=A0 - Added support for SoC expansion block on RD-N2-Cf= g2 platform as >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 well. >> >> Shriram K (1): >> =C2=A0=C2=A0 Platform/Sgi: Initialize additional UART controllers >> >> Vivek Gautam (4): >> =C2=A0=C2=A0 Platform/Sgi: Add SSDT table for Virtio-P9 >> =C2=A0=C2=A0 Platform/Sgi: Enable virtio-p9 device on RD-N2 platform v= ariants >> =C2=A0=C2=A0 Platform/Sgi: Add SSDT table for IO virtualization SoC ex= pansion block >> =C2=A0=C2=A0 Platform/Sgi: Enable SoC expansion block for RD-N2 varian= ts >=20 > For the Virtio-P9 patches: > - Platform/Sgi: Add SSDT table for Virtio-P9 > - Platform/Sgi: Enable virtio-p9 device on RD-N2 platform variants > Reviewed-by: Pierre Gondois > I had some questions for the other patches. Thanks for your review. I will rework the other patches and re-post them. Best regards Vivek >=20 > Regards, > Pierre >=20 >> >> =C2=A0 Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0= 12 +- >> =C2=A0 Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 15 +- >> =C2=A0 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf=C2=A0=C2=A0= =C2=A0 |=C2=A0 15 +- >> =C2=A0 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf=C2=A0=C2=A0= =C2=A0 |=C2=A0 11 +- >> =C2=A0 Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf=C2=A0 |= =C2=A0 10 +- >> =C2=A0 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf=C2=A0 |= =C2=A0=C2=A0 7 +- >> =C2=A0 Platform/ARM/SgiPkg/Include/IoVirtSoCExp.h=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 189=20 >> ++++++++++++++++++++ >> =C2=A0 Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.c=C2=A0=C2=A0= =C2=A0 |=C2=A0 64 ++++++- >> =C2=A0 Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c |=C2=A0= 43 ++++- >> =C2=A0 Platform/ARM/SgiPkg/AcpiTables/SsdtIoVirtSocExp.asl=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 |=C2=A0 96=20 >> ++++++++++ >> =C2=A0 Platform/ARM/SgiPkg/AcpiTables/SsdtRosVirtioP9.asl=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 |=C2=A0 42 +++++ >> =C2=A0 Platform/ARM/SgiPkg/SgiPlatform.dec=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 |=C2=A0 13 +- >> =C2=A0 12 files changed, 503 insertions(+), 14 deletions(-) >> =C2=A0 create mode 100644 Platform/ARM/SgiPkg/Include/IoVirtSoCExp.h >> =C2=A0 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/SsdtIoVirtSoc= Exp.asl >> =C2=A0 create mode 100644 Platform/ARM/SgiPkg/AcpiTables/SsdtRosVirtio= P9.asl >>