From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.1597.1639590183009848801 for ; Wed, 15 Dec 2021 09:43:03 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pierre.gondois@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 12B181435; Wed, 15 Dec 2021 09:43:02 -0800 (PST) Received: from [10.34.129.49] (unknown [10.34.129.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E41EF3F5A1; Wed, 15 Dec 2021 09:43:00 -0800 (PST) From: "PierreGondois" Subject: Re: [edk2-devel] [PATCH v4 2/3] Silicon/ARM/NeoverseN1Soc: Add CCIX root complex support To: devel@edk2.groups.io, khasim.mohammed@arm.com Cc: nd@arm.com, Sami.mujawar@arm.com References: <20211214194356.21005-1-khasim.mohammed@arm.com> <20211214194356.21005-3-khasim.mohammed@arm.com> Message-ID: <8339b711-d230-0199-b94c-7727ff30b8d8@arm.com> Date: Wed, 15 Dec 2021 18:43:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211214194356.21005-3-khasim.mohammed@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable Hi Khassim, Thanks for the new serie. I have some comments about the PCDs: On 12/14/21 8:43 PM, Khasim Mohammed via groups.io wrote: > This patch enables CCIX root complex support by updating > the root complex node info in PciHostBridge library. > The corresponding PCDs are updated. > > Change-Id: I0510b1023aec16365b614d4eaf81858851d9fa28 The 'Change-Id' should be removed I think. > Signed-off-by: Khasim Syed Mohammed > --- > .../ConfigurationManager.c | 6 +- > .../ConfigurationManagerDxe.inf | 4 +- > Platform/ARM/N1Sdp/N1SdpPlatform.dec | 10 ++- > Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 1 - > .../PciHostBridgeLib/PciHostBridgeLib.c | 71 +++++++++++++++++-- > .../PciHostBridgeLib/PciHostBridgeLib.inf | 11 ++- > .../Library/PlatformLib/PlatformLib.inf | 1 + > .../Library/PlatformLib/PlatformLibMem.c | 4 +- > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 10 +-- > 9 files changed, 91 insertions(+), 27 deletions(-) > > diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManag= erDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/Co= nfigurationManagerDxe/ConfigurationManager.c > index 9c91372c11..1998c44e63 100644 > --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/C= onfigurationManager.c > +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/C= onfigurationManager.c > @@ -1047,21 +1047,21 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryI= nfo =3D { > { > // PCIe ECAM > { > - 0x70000000, // Base Address > + FixedPcdGet64 (PcdPcieExpressBaseAddress), // Base Address > 0x0, // Segment Group Number > 0x0, // Start Bus Number > 17 // End Bus Number For the 3 PCI interfaces (PCIe, remote PCI and CCIX), I think we can also= use the Pcds for the min/max bus numbers: gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax I think a Pcd could also be created for each Segment Group Number, as for= instance: gArmNeoverseN1SocTokenSpaceGuid.PcdPcieSegmentGroup Indeed, the segment number is also hard coded in the objects at: Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables= /SsdtRemotePci.asl Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables= /SsdtPci.asl Name (_SEG, Pcd(...))=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // PCI Segment Group number Name (_BBN, Pcd(...))=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 // PCI Base Bus Number > }, > // CCIX ECAM > { > - 0x68000000, // Base Address > + FixedPcdGet32 (PcdCcixExpressBaseAddress), // Base Address > 0x1, // Segment Group Number > 0x0, // Start Bus Number > 17 // End Bus Number > }, > //Remote Chip PCIe ECAM > { > - 0x40070000000, // Base Address > + FixedPcdGet64 (PcdRemotePcieBaseAddress), // Base Address > 0x2, // Segment Group Number > 0x0, // Start Bus Number > 17 // End Bus Number > diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManag= erDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManag= er/ConfigurationManagerDxe/ConfigurationManagerDxe.inf > index 027a4202ff..84543e2f95 100644 > --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/C= onfigurationManagerDxe.inf > +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/C= onfigurationManagerDxe.inf > @@ -76,8 +76,6 @@ > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase > gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate > =20 > - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress > - > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace > gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > =20 > @@ -91,6 +89,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize > @@ -158,6 +157,7 @@ > gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase > =20 > # Remote PCIe > + gArmN1SdpTokenSpaceGuid.PcdRemotePcieBaseAddress > gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation > gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation > gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/= N1SdpPlatform.dec > index 2ab6c20dcc..ed7ea44d0d 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec > @@ -34,9 +34,6 @@ > gArmN1SdpTokenSpaceGuid.PcdRamDiskBase|0x88000000|UINT32|0x00000001 > gArmN1SdpTokenSpaceGuid.PcdRamDiskSize|0x18000000|UINT32|0x00000002 > =20 > - # PCIe > - gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000|UINT32|= 0x00000007 > - > # External memory > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0|UINT64|0x0000002= 9 > =20 > @@ -94,6 +91,7 @@ > gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049 > =20 > # Remote Chip PCIe > - gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UIN= T64|0x0000004A > - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000= |UINT64|0x0000004B > - gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000= |UINT64|0x0000004C > + gArmN1SdpTokenSpaceGuid.PcdRemotePcieBaseAddress|0x40070000000|UINT6= 4|0x0000004A > + gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UIN= T64|0x0000004B > + gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000= |UINT64|0x0000004C > + gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000= |UINT64|0x0000004D > diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/= N1SdpPlatform.dsc > index 7488bdc036..cb2049966c 100644 > --- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > +++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc > @@ -127,7 +127,6 @@ > gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x300C0000 > =20 > # PCIe > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x70000000 > gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 > gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE > =20 > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHost= BridgeLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostB= ridgeLib.c > index 9332939f63..c3a14a6c17 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeL= ib.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeL= ib.c > @@ -1,7 +1,7 @@ > /** @file > * PCI Host Bridge Library instance for ARM Neoverse N1 platform > * > -* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +* Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
> * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -16,6 +16,8 @@ > #include > #include > =20 > +#define ROOT_COMPLEX_NUM 2 > + > GLOBAL_REMOVE_IF_UNREFERENCED > STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[]= =3D { > L"Mem", L"I/O", L"Bus" > @@ -28,7 +30,7 @@ typedef struct { > } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > #pragma pack () > =20 > -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] =3D= { > +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROO= T_COMPLEX_NUM] =3D { > // PCIe > { > { > @@ -51,10 +53,33 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootB= ridgeDevicePath[] =3D { > 0 > } > } > - } > + }, > + //CCIX > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A09), // CCIX > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > }; > =20 > -STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { > +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] =3D { > { > 0, // Segment > 0, // Supports > @@ -90,7 +115,43 @@ STATIC PCI_ROOT_BRIDGE mPciRootBridge[] =3D { > 0 > }, > (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] > - } > + }, > + { > + 1, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfi= gSpace > + FALSE, // ResourceAssigne= d > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttri= butes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { > + // Bus > + FixedPcdGet32 (PcdCcixBusMin), > + FixedPcdGet32 (PcdCcixBusMax) > + }, { > + // Io > + FixedPcdGet64 (PcdCcixIoBase), > + FixedPcdGet64 (PcdCcixIoBase) + FixedPcdGet64 (PcdCcixIoSize) - = 1 > + }, { > + // Mem > + FixedPcdGet32 (PcdCcixMmio32Base), > + FixedPcdGet32 (PcdCcixMmio32Base) + FixedPcdGet32 (PcdCcixMmio32= Size) - 1 > + }, { > + // MemAbove4G > + FixedPcdGet64 (PcdCcixMmio64Base), > + FixedPcdGet64 (PcdCcixMmio64Base) + FixedPcdGet64 (PcdCcixMmio64= Size) - 1 > + }, { > + // PMem > + MAX_UINT64, > + 0 > + }, { > + // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] > + }, > }; > =20 > /** > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHost= BridgeLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHos= tBridgeLib.inf > index 3ff1c592f2..3356c3ad35 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeL= ib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PciHostBridgeLib/PciHostBridgeL= ib.inf > @@ -1,7 +1,7 @@ > ## @file > # PCI Host Bridge Library instance for ARM Neoverse N1 platform. > # > -# Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. > +# Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -42,6 +42,15 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size > =20 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size > + > [Protocols] > gEfiCpuIo2ProtocolGuid > =20 > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.= inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > index 8e2154aadf..96e590cdd8 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > @@ -43,6 +43,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibM= em.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > index 1c4a445c5e..339fa07b32 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > @@ -115,8 +115,8 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTR= IBUTE_DEVICE; > =20 > // PCIe ECAM Configuration Space > - VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPciExpres= sBaseAddress); > - VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPciExpres= sBaseAddress); > + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdPcieExpre= ssBaseAddress); > + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdPcieExpre= ssBaseAddress); > VirtualMemoryTable[Index].Length =3D (FixedPcdGet32 (PcdPci= eBusMax) - > FixedPcdGet32 (PcdPcieB= usMin) + 1) * > SIZE_1MB; > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/= NeoverseN1Soc/NeoverseN1Soc.dec > index eea2d58402..9d7e2e3130 100644 > --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > @@ -46,6 +46,7 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UI= NT64|0x00000010 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT6= 4|0x00000011 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|= 0x00000012 > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieExpressBaseAddress|0x70000000= |UINT64|0x00000013 > =20 > # CCIX > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 > @@ -53,8 +54,8 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000= |UINT32|0x00000019 > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A > - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0= 000001B > - gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000= 001C > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x00FFFFFF|UINT32|0= x0000001B > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x01000000|UINT32|0x00= 00001C > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT= 32|0x00000001D > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|= 0x0000001E > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT= 32|0x00000001F > @@ -68,8 +69,3 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x0000= 1000|UINT32|0x00000027 > =20 > gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT= 64|0x00000029 > - > - # Remote Chip PCIe > - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x4007520= 0000|UINT64|0x0000004A > - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x400= 00000000|UINT64|0x0000004B > - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x400= 00000000|UINT64|0x0000004C Isn't the remote PCIe interface more specific to the Neoverse N1 Soc ? I = think we should keep the gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieXXX PCDs and remove the gArmN1SdpTokenSpaceGuid.PcdRemotePcieXXX ones instead. Also would it be possible to split the patch in 2 parts ? - CCIX root complex support enablement - other PCDs alignement Regards, Pierre