From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8B11721DF808C for ; Mon, 28 Aug 2017 00:12:46 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3D3B67C837; Mon, 28 Aug 2017 07:15:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 3D3B67C837 Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=lersek@redhat.com Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-67.phx2.redhat.com [10.3.116.67]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2F36570C4F; Mon, 28 Aug 2017 07:15:24 +0000 (UTC) To: Star Zeng , edk2-devel@lists.01.org Cc: Jiewen Yao , Eric Dong References: <1503885256-174936-1-git-send-email-star.zeng@intel.com> From: Laszlo Ersek Message-ID: <8394d255-1336-f745-1ed8-37015e8d5795@redhat.com> Date: Mon, 28 Aug 2017 09:15:23 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <1503885256-174936-1-git-send-email-star.zeng@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Mon, 28 Aug 2017 07:15:25 +0000 (UTC) Subject: Re: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Centralize mPhysicalAddressBits definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 07:12:46 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 08/28/17 03:54, Star Zeng wrote: > Originally (before 714c2603018a99a514c42c2b511c821f30ba9cdf), > mPhysicalAddressBits was only defined in X64 PageTbl.c, after > 714c2603018a99a514c42c2b511c821f30ba9cdf, mPhysicalAddressBits is > also defined in Ia32 PageTbl.c, then mPhysicalAddressBits is used in > ConvertMemoryPageAttributes() for address check. > > This patch is to centralize mPhysicalAddressBits definition to > PiSmmCpuDxeSmm.c from Ia32 and X64 PageTbl.c. > > Cc: Jiewen Yao > Cc: Laszlo Ersek > Cc: Eric Dong > Suggested-by: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Star Zeng > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 2 -- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 2 ++ > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 1 - > 3 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > index e88b42d73343..f295c2ebf228 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > @@ -16,8 +16,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > > #include "PiSmmCpuDxeSmm.h" > > -UINT8 mPhysicalAddressBits; > - > /** > Create PageTable for SMM use. > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > index 8e7964271125..282d2e69817c 100755 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c > @@ -114,6 +114,8 @@ SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL; > EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; > UINTN mSmmCpuSmramRangeCount; > > +UINT8 mPhysicalAddressBits; > + > /** > Initialize IDT to setup exception handlers for SMM. > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > index 32385faae470..3dde80f9bad6 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -21,7 +21,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > > LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool); > BOOLEAN m1GPageTableSupport = FALSE; > -UINT8 mPhysicalAddressBits; > BOOLEAN mCpuSmmStaticPageTable; > > /** > Reviewed-by: Laszlo Ersek Thanks! Laszlo