Re: [edk2-devel] [edk2] DxeIpl : create page table, occupied too much memory range

["Andrew Fish" <afish@apple.com>]

> On Sep 18, 2019, at 3:50 AM, Tiger Liu(BJ-RD) <tigerliu@zhaoxin.com> wrote:
> 
> Hi, Laszlo:
> Thanks for your reply!
> 
> Is Using PcdUse5LevelPageTable also a method to reduce paging table's memory requirement?
> 

Tiger,

No the 5-level page tables [1] are about increasing the size of the virtual addresses from 48 bits (256 terabytes) to 57 bits (128 petabytes). On x86 there are noncanonical addresses [2] in the middle of the virtual memory space that will cause a GP fault if they are used since they can not be mapped by page tables.  The 5-level page table decreases the amount of noncanonical addressess in the virtual memory map, since the 5th level allows you to map more virtual addresses. I think from an EFI perspective you likely only add a single page table entry unless your CPU supports more than 256 terabytes of physical address space. 

> I find PcdUse1GPageTable's default value is false, why?

The people who work for CPU companies will know more than me, but I seem to remember that 1GB page tables are common on modern server CPUs, but not on client CPUs. So I guess the PCD is just to remove a check that is likely to fail [3]. If your system supports 1GB pages you can set PcdUse1GPageTable to TRUE in your platforms DSC file. 

Given EFI is identity mapped (Virtual address == Physical address) and Long Mode requires that paging is enabled you need page tables for any physical address that is decoded by your chipset or memory controller (memory or memory mapped IO). 

If you look at this code [4] you will see you can configure how much of the address space requires page tables via the EFI_HOB_TYPE_CPU, if that HOB is not present a CPU ID instruction is used to ask the processor how much physical addressing it supports, and if that CPU ID feature is not present you get the old answer of 36-bits. 

So if you are trying to minimized page table generation you need to set EFI_HOB_TYPE_CPU.SizeOfMemorySpace to a value that matches the highest memory or memory mapped IO physical addresses you platform supports. Basically it does not matter how much physical addressing your CPU supports if nothing in your system is decoded by some of the upper address bits. PcdUse1GPageTable is only going to help you if your CPU supports it. 

> 
> PcdUse5LevelPageTable's default value is true, and DxeIpl module will create 5-level paging for Dxe's long mode?
> 

As I mentioned you only need the 5 level page tables if your system has memory or memory mapped IO at an address greater than 256 terabytes (48-bits).

[1] https://en.wikipedia.org/wiki/Intel_5-level_paging
[2] https://en.wikipedia.org/wiki/X86-64
[3] https://github.com/tianocore/edk2/blob/master/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c#L667
[4] https://github.com/tianocore/edk2/blob/master/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c#L679

Thanks,

Andrew Fish

> Best wishes,
> 
> -----邮件原件-----
> 发件人: Laszlo Ersek <lersek@redhat.com>
> 发送时间: 2019年9月17日 20:07
> 收件人: devel@edk2.groups.io; Tiger Liu(BJ-RD) <TigerLiu@zhaoxin.com>
> 主题: Re: [edk2-devel] [edk2] DxeIpl : create page table, occupied too much memory range
> 
> On 09/17/19 13:08, Tiger Liu(BJ-RD) wrote:
>> Hi, Expert:
>> I have a question about creating page table.
>> If a CPU support 48bit physical address line, then creating page tables(Page size=2MB) will occupy too much memory region.
>> 
>> Now, developer could only use PcdUse1GPageTable to avoid occupy too much memory region?
> 
> Not only. See <https://bugzilla.tianocore.org/show_bug.cgi?id=2008>.
> 
> Thanks
> Laszlo
> 
> 
> 保密声明：
> 本邮件含有保密或专有信息，仅供指定收件人使用。严禁对本邮件或其内容做任何未经授权的查阅、使用、复制或转发。
> CONFIDENTIAL NOTE:
> This email contains confidential or legally privileged information and is for the sole use of its intended recipient. Any unauthorized review, use, copying or forwarding of this email or the content of this email is strictly prohibited.
> 
> 
>