From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.groups.io with SMTP id smtpd.web11.9924.1626091488717961482 for ; Mon, 12 Jul 2021 05:04:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@akeo-ie.20150623.gappssmtp.com header.s=20150623 header.b=A0iU9um/; spf=pass (domain: akeo.ie, ip: 209.85.128.46, mailfrom: pete@akeo.ie) Received: by mail-wm1-f46.google.com with SMTP id j25-20020a05600c1c19b02902269686f585so1045483wms.0 for ; Mon, 12 Jul 2021 05:04:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=yq6vG7fr4JxM5fwBrW/2MlNAxzBJZ11C43uNZJdmX6I=; b=A0iU9um/bd6UkkViN138FpCKmPQUwDUtsvcwaAd6VQuFk5MzorLgAx+4YRNEY9tv7U ica50M0PE5JzsBs/kUt61vehdiC/t27+D5htx8dMq5iqoPENhxJhwZ+hVB3EB0SJ62UW QXEDu+r13LjIXPej8CCzK7+T0qxCTWrkcOEI2CJKyPDHYHr67Nhm8aNUMMs7w3k6YlW8 ngvOicXXdaezajZi8V8uWKoJPd5NKH9wwOhfukjdqvjjomZw1aG7pm6Rd81cKBaUhcDR G1GCn+ucB/bkwcuh2Jquie+9Uc2wFqeU0vEPyJTF5PBgE0nre9+YTIedIQbf8+HeSaT+ yNIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=yq6vG7fr4JxM5fwBrW/2MlNAxzBJZ11C43uNZJdmX6I=; b=M9CA6uC1q1EtdVARCJ/QbcZU2a72fDVjFEPh7z61xsR0vZ98iwJzWMqXzKNFFG21dM mI0h+/cUkL/Ing5Z3aXjnKeLt4AHi8fOVubwbU03s9RogE9lvkNYPvWicmlGIdj4LNIY qHNxsTWlYzNAO5LUXjQNMuVUUdAj6qUwjRn95YrALlA6oJKj4lGT8WzUD7RfvWYM68Rl ZiFi+ez8dtVSaTSORWwt2xlAzMruG74qsHWl/9KapDBqJq66hF+IPuhFWRjEu0eIgSBL 7mSfu4shLsoeQth7K3dt/dMURGEihdkmSKwCO2J92wEgNHD+a6pcf43xENtT97SdhcNV izTQ== X-Gm-Message-State: AOAM531ieQ9m5cNXMofgv1JzsjN8Wt9cOlTvO7dRNoCBcYISjPAlCRzw x7JGp5h4L6G4DrYOV9PJrVrgGw== X-Google-Smtp-Source: ABdhPJytUnRy3F8X03Zxh88Jet40tKl+tx9EoFu5ZbKGbdRqrdHBlO9T7CAVQj/TnR4EUxTKZ3WEEw== X-Received: by 2002:a05:600c:2315:: with SMTP id 21mr18938932wmo.35.1626091486803; Mon, 12 Jul 2021 05:04:46 -0700 (PDT) Return-Path: Received: from [10.0.0.122] ([84.203.68.81]) by smtp.googlemail.com with ESMTPSA id 204sm12772954wma.30.2021.07.12.05.04.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Jul 2021 05:04:46 -0700 (PDT) Subject: Re: [edk2-devel] [PATCH v4] BaseTools GenFw: Add support for RISCV GOT/PLT relocations To: devel@edk2.groups.io, sunilvl@ventanamicro.com Cc: Abner Chang , Daniel Schaefer , Bob Feng , Liming Gao , Yuwei Chen , Heinrich Schuchardt References: <20210624132531.54062-1-sunilvl@ventanamicro.com> From: "Pete Batard" Message-ID: <84b68a87-dbc9-67e4-3475-3bc0e0ddf2cf@akeo.ie> Date: Mon, 12 Jul 2021 13:04:44 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210624132531.54062-1-sunilvl@ventanamicro.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Since I was also impacted by this in the RISC-V NTFS driver, and I can vouch that this patch does produce a functional executable when tested with QEMU, I'll add my T-b as well. On 2021.06.24 14:25, Sunil V L wrote: > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096 > > This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 > relocations generated by PIE enabled compiler. This also needed > changes to R_RISCV_32 and R_RISCV_64 relocations as explained in > https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710 > > Changes in v4: > - Fixed the typecast issue found by VS2019. > > Changes in v3: > - Added the comments to address Liming's feedback. > > Changes in v2: > - Addressed Daniel's comment on formatting > > Testing: > 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. > 2) Debian 10.2.0 and booted QEMU virt model. > 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. > > Signed-off-by: Sunil V L > > Acked-by: Abner Chang > Reviewed-by: Daniel Schaefer > Tested-by: Daniel Schaefer > > Cc: Bob Feng > Cc: Liming Gao > Cc: Yuwei Chen > Cc: Heinrich Schuchardt > --- > BaseTools/Source/C/GenFw/Elf64Convert.c | 59 ++++++++++++++++++++++--- > 1 file changed, 53 insertions(+), 6 deletions(-) > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c > index d097db8632..f86be95fbb 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; > STATIC UINT8 *mRiscVPass1Targ = NULL; > > STATIC Elf_Shdr *mRiscVPass1Sym = NULL; > > STATIC Elf64_Half mRiscVPass1SymSecIndex = 0; > > +STATIC INT32 mRiscVPass1Offset; > > +STATIC INT32 mRiscVPass1GotFixup; > > > > // > > // Initialization Function > > @@ -473,17 +475,18 @@ WriteSectionRiscV64 ( > { > > UINT32 Value; > > UINT32 Value2; > > + Elf64_Addr GOTEntryRva; > > > > switch (ELF_R_TYPE(Rel->r_info)) { > > case R_RISCV_NONE: > > break; > > > > case R_RISCV_32: > > - *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); > > + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > > break; > > > > case R_RISCV_64: > > - *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]; > > + *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; > > break; > > > > case R_RISCV_HI20: > > @@ -533,6 +536,18 @@ WriteSectionRiscV64 ( > mRiscVPass1SymSecIndex = 0; > > break; > > > > + case R_RISCV_GOT_HI20: > > + GOTEntryRva = (Sym->st_value - Rel->r_offset); > > + mRiscVPass1Offset = RV_X(GOTEntryRva, 0, 12); > > + Value = (UINT32)RV_X(GOTEntryRva, 12, 20); > > + *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12)); > > + > > + mRiscVPass1Targ = Targ; > > + mRiscVPass1Sym = SymShdr; > > + mRiscVPass1SymSecIndex = Sym->st_shndx; > > + mRiscVPass1GotFixup = 1; > > + break; > > + > > case R_RISCV_PCREL_HI20: > > mRiscVPass1Targ = Targ; > > mRiscVPass1Sym = SymShdr; > > @@ -545,11 +560,17 @@ WriteSectionRiscV64 ( > if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { > > int i; > > Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); > > - Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > > - if(Value & (RISCV_IMM_REACH/2)) { > > - Value |= ~(RISCV_IMM_REACH-1); > > + > > + if(mRiscVPass1GotFixup) { > > + Value = (UINT32)(mRiscVPass1Offset); > > + } else { > > + Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); > > + if(Value & (RISCV_IMM_REACH/2)) { > > + Value |= ~(RISCV_IMM_REACH-1); > > + } > > } > > Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex]; > > + > > if(-2048 > (INT32)Value) { > > i = (((INT32)Value * -1) / 4096); > > Value2 -= i; > > @@ -569,12 +590,35 @@ WriteSectionRiscV64 ( > } > > } > > > > - *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); > > + if(mRiscVPass1GotFixup) { > > + *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20) > > + | (RV_X(*(UINT32*)Targ, 0, 20)); > > + // Convert LD instruction to ADDI > > + // > > + // |31 20|19 15|14 12|11 7|6 0| > > + // |-----------------------------------------| > > + // |imm[11:0] | rs1 | 011 | rd | 0000011 | LD > > + // ----------------------------------------- > > + > > + // |-----------------------------------------| > > + // |imm[11:0] | rs1 | 000 | rd | 0010011 | ADDI > > + // ----------------------------------------- > > + > > + // To convert, let's first reset bits 12-14 and 0-6 using ~0x707f > > + // Then modify the opcode to ADDI (0010011) > > + // All other fields will remain same. > > + > > + *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13); > > + } else { > > + *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); > > + } > > *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); > > } > > mRiscVPass1Sym = NULL; > > mRiscVPass1Targ = NULL; > > mRiscVPass1SymSecIndex = 0; > > + mRiscVPass1Offset = 0; > > + mRiscVPass1GotFixup = 0; > > break; > > > > case R_RISCV_ADD64: > > @@ -586,6 +630,7 @@ WriteSectionRiscV64 ( > case R_RISCV_GPREL_I: > > case R_RISCV_GPREL_S: > > case R_RISCV_CALL: > > + case R_RISCV_CALL_PLT: > > case R_RISCV_RVC_BRANCH: > > case R_RISCV_RVC_JUMP: > > case R_RISCV_RELAX: > > @@ -1528,6 +1573,7 @@ WriteRelocations64 ( > case R_RISCV_GPREL_I: > > case R_RISCV_GPREL_S: > > case R_RISCV_CALL: > > + case R_RISCV_CALL_PLT: > > case R_RISCV_RVC_BRANCH: > > case R_RISCV_RVC_JUMP: > > case R_RISCV_RELAX: > > @@ -1537,6 +1583,7 @@ WriteRelocations64 ( > case R_RISCV_SET16: > > case R_RISCV_SET32: > > case R_RISCV_PCREL_HI20: > > + case R_RISCV_GOT_HI20: > > case R_RISCV_PCREL_LO12_I: > > break; > > > Tested-by: Pete Batard