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From: "Laszlo Ersek" <lersek@redhat.com>
To: devel@edk2.groups.io, ray.ni@intel.com, "Yao,
	Jiewen" <jiewen.yao@intel.com>
Cc: "Dong, Eric" <eric.dong@intel.com>
Subject: Re: [edk2-devel] [PATCH 3/3] UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports
Date: Fri, 28 Jun 2019 17:32:11 +0200	[thread overview]
Message-ID: <84f54096-6fc4-8102-fcff-8d428071563b@redhat.com> (raw)
In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5C1F4B96@SHSMSX104.ccr.corp.intel.com>

On 06/28/19 09:27, Ni, Ray wrote:
> Jiewen,
> I tested the above 2^48 memory address access in SMM environment to ensure no GP fault.
> 
> The code is internally used for a while and this patch is to upstream the code to edk2 repo.

I've tagged this for regression-testing (without 5 level paging) in
OVMF. It might take a while.

I'll also ask around if I can test it in a 5-level paging environment
(on KVM) too.

Thanks
Laszlo

  reply	other threads:[~2019-06-28 15:32 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-28  6:46 [PATCH 0/3] Enable 5 level paging when CPU supports Ni, Ray
2019-06-28  6:46 ` [PATCH 1/3] UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM Ni, Ray
2019-06-28  6:46 ` [PATCH 2/3] MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging Ni, Ray
2019-06-28  6:47 ` [PATCH 3/3] UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports Ni, Ray
2019-06-28  7:18   ` [edk2-devel] " Yao, Jiewen
2019-06-28  7:27     ` Ni, Ray
2019-06-28 15:32       ` Laszlo Ersek [this message]
2019-06-28 15:36   ` Laszlo Ersek
2019-07-01 12:44   ` Laszlo Ersek
2019-07-02 14:44     ` Ni, Ray
2019-07-02 15:18       ` Laszlo Ersek
2019-07-02 15:20         ` Laszlo Ersek
2019-07-03 10:08           ` Laszlo Ersek

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