From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2CD092194D387 for ; Wed, 17 Oct 2018 20:08:49 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Oct 2018 20:08:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,393,1534834800"; d="scan'208";a="98401786" Received: from ray-dev.ccr.corp.intel.com (HELO [10.239.9.11]) ([10.239.9.11]) by fmsmga004.fm.intel.com with ESMTP; 17 Oct 2018 20:08:48 -0700 To: Eric Dong , edk2-devel@lists.01.org Cc: Laszlo Ersek References: <20181017021635.14972-1-eric.dong@intel.com> <20181017021635.14972-2-eric.dong@intel.com> From: "Ni, Ruiyu" Message-ID: <86680bbc-e7c1-bb8c-4d6e-046c25020af5@Intel.com> Date: Thu, 18 Oct 2018 11:10:01 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20181017021635.14972-2-eric.dong@intel.com> Subject: Re: [Patch v2 1/6] UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Oct 2018 03:08:50 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 10/17/2018 10:16 AM, Eric Dong wrote: > v2 changes: > 1. Add more description about why we do this change. > 2. Change structure field type from pointer to EFI_PHYSICAL_ADDRESS because it will > be share between PEI and DXE. > > In order to support semaphore related logic, add new definition for it. > > In a system which has multiple cores, current set register value task costs huge times. > After investigation, current set MSR task costs most of the times. Current logic uses > SpinLock to let set MSR task as an single thread task for all cores. Because MSR has > scope attribute which may cause GP fault if multiple APs set MSR at the same time, > current logic use an easiest solution (use SpinLock) to avoid this issue, but it will > cost huge times. > > In order to fix this performance issue, new solution will set MSRs base on their scope > attribute. After this, the SpinLock will not needed. Without SpinLock, new issue raised > which is caused by MSR dependence. For example, MSR A depends on MSR B which means MSR A > must been set after MSR B has been set. Also MSR B is package scope level and MSR A is > thread scope level. If system has multiple threads, Thread 1 needs to set the thread level > MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for thread 1 > and thread 2 like below: > > Thread 1 Thread 2 > MSR B N Y > MSR A Y Y > > If driver don't control execute MSR order, for thread 1, it will execute MSR A first, but > at this time, MSR B not been executed yet by thread 2. system may trig exception at this > time. > > In order to fix the above issue, driver introduces semaphore logic to control the MSR > execute sequence. For the above case, a semaphore will be add between MSR A and B for > all threads. Semaphore has scope info for it. The possible scope value is core or package. > For each thread, when it meets a semaphore during it set registers, it will 1) release > semaphore (+1) for each threads in this core or package(based on the scope info for this > semaphore) 2) acquire semaphore (-1) for all the threads in this core or package(based > on the scope info for this semaphore). With these two steps, driver can control MSR > sequence. Sample code logic like below: > > // > // First increase semaphore count by 1 for processors in this package. > // > for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) { > LibReleaseSemaphore ((UINT32 *) &SemaphorePtr[PackageOffset + ProcessorIndex]); > } > // > // Second, check whether the count has reach the check number. > // > for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) { > LibWaitForSemaphore (&SemaphorePtr[ApOffset]); > } > > Platform Requirement: > 1. This change requires register MSR setting base on MSR scope info. If still register MSR > for all threads, exception may raised. > > Known limitation: > 1. Current CpuFeatures driver supports DXE instance and PEI instance. But semaphore logic > requires Aps execute in async mode which is not supported by PEI driver. So CpuFeature > PEI instance not works after this change. We plan to support async mode for PEI in phase > 2 for this task. > > Cc: Ruiyu Ni > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eric Dong > --- > UefiCpuPkg/Include/AcpiCpuData.h | 45 +++++++++++++++++++++++++++++++++++++++- > 1 file changed, 44 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h > index 9e51145c08..f1439dcf9a 100644 > --- a/UefiCpuPkg/Include/AcpiCpuData.h > +++ b/UefiCpuPkg/Include/AcpiCpuData.h > @@ -22,9 +22,42 @@ typedef enum { > Msr, > ControlRegister, > MemoryMapped, > - CacheControl > + CacheControl, > + // > + // Semaphore type used to control the execute sequence of the Msr. > + // It will be insert between two Msr which has execute dependence. > + // > + Semaphore > } REGISTER_TYPE; > > +// > +// CPU information. > +// > +typedef struct { > + // > + // Record the package count in this CPU. > + // > + UINT32 PackageCount; > + // > + // Record the max core count in this CPU. > + // Different packages may have different core count, this value > + // save the max core count in all the packages. > + // > + UINT32 MaxCoreCount; > + // > + // Record the max thread count in this CPU. > + // Different cores may have different thread count, this value > + // save the max thread count in all the cores. > + // > + UINT32 MaxThreadCount; > + // > + // This fild is an pointer type which point to an array. > + // This array used to save the valid cores in different packages in this CPU. > + // The array count is the package number in this CPU. > + // > + EFI_PHYSICAL_ADDRESS ValidCoresPerPackages; ValidCoreCountPerPackage? Using the new name can tell people that this array holds the core *count*. > +} CPU_STATUS_INFORMATION; > + > // > // Element of register table entry > // > @@ -147,6 +180,16 @@ typedef struct { > // provided. > // > UINT32 ApMachineCheckHandlerSize; > + // > + // CPU information which is required when set the register table. > + // > + CPU_STATUS_INFORMATION CpuStatus; > + // > + // Location info for each AP. > + // It points to an array which saves all APs location info in this CPU. > + // The array count is the AP count in this CPU. > + // > + EFI_PHYSICAL_ADDRESS ApLocation; > } ACPI_CPU_DATA; > > #endif > -- Thanks, Ray