From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=marc.zyngier@arm.com; receiver=edk2-devel@lists.01.org Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 8FA2E21E49051 for ; Wed, 14 Mar 2018 00:38:52 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6D98D1596; Wed, 14 Mar 2018 00:45:14 -0700 (PDT) Received: from big-swifty.misterjones.org (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EE1E23F53D; Wed, 14 Mar 2018 00:45:12 -0700 (PDT) Date: Wed, 14 Mar 2018 07:45:10 +0000 Message-ID: <86a7vbaynt.wl-marc.zyngier@arm.com> From: Marc Zyngier To: Guo Heyi Cc: edk2-devel@lists.01.org, Yi Li , Leif Lindholm , Ard Biesheuvel In-Reply-To: <20180314002509.GE96299@SZX1000114654> References: <1520901090-96694-1-git-send-email-heyi.guo@linaro.org> <1520901090-96694-2-git-send-email-heyi.guo@linaro.org> <0403f2bf-d6a8-b101-73a2-949946f71e46@arm.com> <20180314002509.GE96299@SZX1000114654> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/25.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Organization: ARM Ltd MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Subject: Re: [PATCH v2 1/1] ArmPkg/TimerDxe: Add ISB for timer compare value reload X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Mar 2018 07:38:52 -0000 Content-Type: text/plain; charset=US-ASCII On Wed, 14 Mar 2018 00:25:09 +0000, Guo Heyi wrote: > > On Tue, Mar 13, 2018 at 09:33:33AM +0000, Marc Zyngier wrote: > > On 13/03/18 00:31, Heyi Guo wrote: > > > If timer interrupt is level sensitive, reloading timer compare > > > register has a side effect of clearing GIC pending status, so a "ISB" > > > is needed to make sure this instruction is executed before enabling > > > CPU IRQ, or else we may get spurious timer interrupts. > > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > Signed-off-by: Heyi Guo > > > Signed-off-by: Yi Li > > > Cc: Leif Lindholm > > > Cc: Ard Biesheuvel > > > Cc: Marc Zyngier > > > --- > > > > > > Notes: > > > v2: > > > - Use ISB instead of DSB [Marc] > > > - Update commit message accordingly. > > > > > > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > index 33d7c922221f..32abee8726a0 100644 > > > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > @@ -337,6 +337,7 @@ TimerInterruptHandler ( > > > > > > // Set next compare value > > > ArmGenericTimerSetCompareVal (CompareValue); > > > + ArmInstructionSynchronizationBarrier (); > > > ArmGenericTimerEnableTimer (); > > > } > > > > Sorry for being pedantic here, but it would make more sense if ISB was > > placed after the enabling of the timer. Otherwise, you only force the > > update of the comparator. But on the other hand, the timer was never > > disabled the first place, in which case you'd wonder why you're trying > > to enable it again. > Yes, I also had such question and hesitated at this place :) > > > > So either you leave the ISB here and remove the enable call, or move the > > ISB after the enable. > > If we are going to remove the enable call, is it better to be changed in a > separate patch? It seems not related with adding ISB, though it is only a > one-line change. I guess a separate patch doesn't hurt, but that's for Ard and Leif to decide. Thanks, M. -- Jazz is not dead, it just smell funny.