From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web12.32193.1643637184097367602 for ; Mon, 31 Jan 2022 05:53:04 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=S+hMRKpb; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: maz@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 43F71612B3; Mon, 31 Jan 2022 13:53:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AC167C340E8; Mon, 31 Jan 2022 13:53:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1643637182; bh=san2srlzfniy/P8/KEN8dlJPmUPRJVe/n+Y7nQg296g=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=S+hMRKpbP82OWDiJfuF6vYK2cEC3d6axV0kPLdCv++Qa3rGy2m6OvOPiJjkdnoXye 3l88LfCdhKPdt87AdOvvtvzCwDEfHPDLxEl3fV+wwIdw/pGqw1fGlLjN8KQ6p1dmD1 VO30QoleeUw4cGoHrpKQMrsM+olPP1vKIkoBf4m5Z2Ax6RQxfzvjnJaqNbtCJMeZSr VZHRerH0o0MVCk5D3C9tsz+cUvy0OyW89WD664YTCURZ6rKxNgv3D0hOyoQ0R6Kw4U dvJI2/u2L8b1FvOZDgPrnpdlhhmzcwhit0kt/8mjlNmWYxiE5g/7lJpIW/N3I89CrD 2YJLx6KtGF1gw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nEX76-004Mzc-9I; Mon, 31 Jan 2022 13:53:00 +0000 Date: Mon, 31 Jan 2022 13:52:59 +0000 Message-ID: <87k0eg57wk.wl-maz@kernel.org> From: Marc Zyngier To: Pierre Gondois Cc: Ard Biesheuvel , edk2-devel-groups-io , Ard Biesheuvel , Sami Mujawar Subject: Re: [PATCH v3 3/8] DynamicTablesPkg: AcpiSsdtPcieLibArm: Fix _PRT description In-Reply-To: <7f29990d-7ce4-8d4e-5ba3-8eea8a960afe@arm.com> References: <20220128154103.20752-1-Pierre.Gondois@arm.com> <20220128154103.20752-4-Pierre.Gondois@arm.com> <87sft6xv2h.wl-maz@kernel.org> <7f29990d-7ce4-8d4e-5ba3-8eea8a960afe@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: pierre.gondois@arm.com, ardb@kernel.org, devel@edk2.groups.io, ardb+tianocore@kernel.org, sami.mujawar@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset=US-ASCII On Mon, 31 Jan 2022 12:59:11 +0000, Pierre Gondois wrote: > > Hi, > > On 1/29/22 7:20 PM, Marc Zyngier wrote: > > On Sat, 29 Jan 2022 15:52:02 +0000, > > Ard Biesheuvel wrote: > >> > >> (+ Marc) > >> > >> On Fri, 28 Jan 2022 at 16:41, wrote: > >>> > >>> From: Pierre Gondois > >>> > >>> In ACPI 6.4, s6.2.13, _PRT objects describing PCI legacy interrupts > >>> can be defined following 2 models. > >>> In the first model, a _SRS object must be described to modify the PCI > >>> interrupt. The _CRS and _PRS object allows to describe the PCI > >>> interrupt (level/edge triggered, active high/low). > >>> In the second model, the PCI interrupt cannot be described with a > >>> similar granularity. PCI interrupts are by default level triggered, > >>> active low. > >>> > >>> GicV2 SPI interrupts are level or edge triggered, active high. To > >>> correctly describe PCI interrupts, the first model is used, even though > >>> Arm Base Boot Requirements v1.0 requires to use the second mode. > >>> > >> > >> There are two different issues here: > >> > >> - using separate 'interrupt link' device objects with an Interrupt() > >> resource rather than a simple GSIV number > >> - whether _PRS and _SRS need to be implemented on those link objects. > >> > >> The latter is simply not true - _PRS and _SRS are optional, and > >> pointless if there is only a single possible value, so there is really > >> no need to add them here. > >> > >> As for the choice between the link object or the GSIV number: I don't > >> think INTx interrupts on ARM systems are actually level low, and the > >> GSIV option is widely used, also in platforms that exist in > >> edk2-platforms, without any reported issues. > >> > >> I've cc'ed Marc, perhaps he can shed some light on this, but I'd > >> prefer to stick to the GSIV approach if we can, as it is much simpler. > > > > I don't immediately see the point either. Yes, the GIC only supports > > level-high interrupts. However, all the PCIe implementations connected > > to it are inverting the level. If they don't, that's even simpler (the > > HW is broken). > > > > Is this to address an apparent disconnect with the spec? > > > > [...] > > > > 1. _PRS/_SRS methods > I agree they are optional and meaningless here as interrupts are not dynamically configurable. > However linux is checking that: > - the interrupt used in _CRS is one of the possible interrupts advertised in _PRS. If not, then a warning is issued and the interrupt is not used. > - the _SRS method is present. If not, setting the interrupt fails. > If _PRS and _SRS method are really optional, it seems these checks should not happen. > For now, using a link object without _PRS/_SRS doesn't work. > > Note: > The first check was initially done because an invalid interrupt was advertised in _CRS when valid interrupts were available in _PRS. > https://bugzilla.kernel.org/show_bug.cgi?id=2665 > > 2. GSIV vs link object > The fist motivation was to accurately describe the interrupts. > Even though GIC interrupts must be active high, PCI interrupts are > active low by default (according to spec), and the GSIV model > doesn't allow to describe the polarity/activation state. And any operating system that groks ACPI on arm64 already knows about this quirks. > Another point that came out is that in linux, GSIV interrupts for > PCI are configured as level triggered by default. That's part of the PCI spec. INTx is level triggered, no ifs, no buts. Otherwise, you can't implement interrupt sharing, which legacy PCI requires with INTx. So Linux has nothing to do with this. > From "Base System Architecture 1.0", sE.4 and sE.6, PCI interrupts > can be level or edge triggered. You are confusing MSIs, which *MUST* be edge, and INTx which *MUST* be level. These are two very different thing, and you really should not conflate the two. > More specifically, KvmTool configures PCI interrupts as edge > triggered. Well, that's a gross bug in kvmtool. I guess that it doesn't really matter for virtio devices, but this should be fixed. > So the only way to describe an edge interrupt is to use a link object. MSIs should never be described in ACPI, as they are entirely SW programmable (there is no static allocation). Only INTx must be described, and that's strictly level. Thanks, M. -- Without deviation from the norm, progress is not possible.