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dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; Received: from AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) by AS8PR08MB6166.eurprd08.prod.outlook.com (2603:10a6:20b:296::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.26; Tue, 18 May 2021 11:05:19 +0000 Received: from AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::80cb:878d:c8f1:2688]) by AS8PR08MB6806.eurprd08.prod.outlook.com ([fe80::80cb:878d:c8f1:2688%7]) with mapi id 15.20.4129.031; Tue, 18 May 2021 11:05:19 +0000 Subject: Re: [PATCH v3 3/5] GenFv: Arm: support images entered in Thumb mode To: Etienne Carriere , devel@edk2.groups.io Cc: Achin Gupta , Ard Biesheuvel , Jiewen Yao , Leif Lindholm , Sughosh Ganu , Bob Feng , Liming Gao , nd@arm.com References: <20210517074054.30281-1-etienne.carriere@linaro.org> <20210517074054.30281-3-etienne.carriere@linaro.org> From: "Sami Mujawar" Message-ID: <892efe8d-254f-9c76-6d75-90f046a6cdb1@arm.com> Date: Tue, 18 May 2021 12:05:18 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2021 11:05:34.6336 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a1c1059-2cd0-4ac6-2582-08d919ecdc44 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT050.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB7015 Content-Type: multipart/alternative; boundary="------------11D7D1C84D404635858C937D" Content-Language: en-GB --------------11D7D1C84D404635858C937D Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Hi Etienne, Thank you for this patch. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 17/05/2021 08:40 AM, Etienne Carriere wrote: > Change GenFv for Arm architecture to generate a specific jump > instruction as image entry instruction, when the target entry label > is assembled with Thumb instruction set. This is possible since > SecCoreEntryAddress value fetched from the PE32 has its LSBit set when > the entry instruction executes in Thumb mode. > > Cc: Bob Feng > Cc: Liming Gao > Cc: Achin Gupta > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Sughosh Ganu > Signed-off-by: Etienne Carriere > --- > Changes since v2: > - Fix missing parentheses in expression. > > Changes since v1: > - Fix typos in commit log and inline comments > - Change if() test operand to be an explicit boolean > --- > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++----- > 1 file changed, 29 insertions(+), 9 deletions(-) > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > index 6e296b8ad6..6cf9c84e73 100644 > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include "FvLib.h" > #include "PeCoffLib.h" > > -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION 0xEB000000 > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000 > > +/* > + * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode. > + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate) > + * BLX (encoding A2) branches to offset in Thumb instruction set mode. > + * BL (encoding A1) branches to offset in Arm instruction set mode. > + */ > +#define ARM_JUMP_OFFSET_MAX 0xffffff > +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2)) > + > +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \ > + (((Imm32) & (1 << 1)) << (24 - 1)) | \ > + (((Imm32) >> 2) & 0x7fffff)) > +#define ARM_JUMP_TO_THUMB(Offset) _ARM_JUMP_TO_THUMB((Offset) - 8) > + > +/* > + * Arm instruction to retrun from exception (MOVS PC, LR) > + */ > +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E > + > BOOLEAN mArm = FALSE; > BOOLEAN mRiscV = FALSE; > STATIC UINT32 MaxFfsAlignment = 0; > @@ -2203,23 +2221,25 @@ Returns: > // if we found an SEC core entry point then generate a branch instruction > // to it and populate a debugger SWI entry as well > if (UpdateVectorSec) { > + UINT32 EntryOffset; > > VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector"); > > - // B SecEntryPoint - signed_immed_24 part +/-32MB offset > - // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8 > - ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) >> 2; > + EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress); > > - if (ResetVector[0] > 0x00FFFFFF) { > - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV"); > + if (EntryOffset > ARM_JUMP_OFFSET_MAX) { > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of the start of the FV"); > return EFI_ABORTED; > } > > - // Add opcode for an unconditional branch with no link. i.e.: " B SecEntryPoint" > - ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION; > + if ((SecCoreEntryAddress & 1) != 0) { > + ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset); > + } else { > + ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset); > + } > > // SWI handler movs pc,lr. Just in case a debugger uses SWI > - ResetVector[2] = 0xE1B0F07E; > + ResetVector[2] = ARM_RETURN_FROM_EXCEPTION; > > // Place holder to support a common interrupt handler from ROM. > // Currently not supported. For this to be used the reset vector would not be in this FV --------------11D7D1C84D404635858C937D Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 7bit

Hi Etienne,

Thank you for this patch.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar


On 17/05/2021 08:40 AM, Etienne Carriere wrote:
Change GenFv for Arm architecture to generate a specific jump
instruction as image entry instruction, when the target entry label
is assembled with Thumb instruction set. This is possible since
SecCoreEntryAddress value fetched from the PE32 has its LSBit set when
the entry instruction executes in Thumb mode.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Achin Gupta <achin.gupta@arm.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
---
Changes since v2:
- Fix missing parentheses in expression.

Changes since v1:
- Fix typos in commit log and inline comments
- Change if() test operand to be an explicit boolean
---
 BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++-----
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 6e296b8ad6..6cf9c84e73 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include "FvLib.h"
 #include "PeCoffLib.h"
 
-#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION       0xEB000000
 #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION      0x14000000
 
+/*
+ * Arm instruction to jump to Fv entry instruction in Arm or Thumb mode.
+ * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX (immediate)
+ * BLX (encoding A2) branches to offset in Thumb instruction set mode.
+ * BL (encoding A1) branches to offset in Arm instruction set mode.
+ */
+#define ARM_JUMP_OFFSET_MAX        0xffffff
+#define ARM_JUMP_TO_ARM(Offset)    (0xeb000000 | ((Offset - 8) >> 2))
+
+#define _ARM_JUMP_TO_THUMB(Imm32)  (0xfa000000 | \
+                                    (((Imm32) & (1 << 1)) << (24 - 1)) | \
+                                    (((Imm32) >> 2) & 0x7fffff))
+#define ARM_JUMP_TO_THUMB(Offset)  _ARM_JUMP_TO_THUMB((Offset) - 8)
+
+/*
+ * Arm instruction to retrun from exception (MOVS PC, LR)
+ */
+#define ARM_RETURN_FROM_EXCEPTION  0xE1B0F07E
+
 BOOLEAN mArm = FALSE;
 BOOLEAN mRiscV = FALSE;
 STATIC UINT32   MaxFfsAlignment = 0;
@@ -2203,23 +2221,25 @@ Returns:
     // if we found an SEC core entry point then generate a branch instruction
     // to it and populate a debugger SWI entry as well
     if (UpdateVectorSec) {
+      UINT32                    EntryOffset;
 
       VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC vector");
 
-      // B SecEntryPoint - signed_immed_24 part +/-32MB offset
-      // on ARM, the PC is always 8 ahead, so we're not really jumping from the base address, but from base address + 8
-      ResetVector[0] = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress - 8) >> 2;
+      EntryOffset = (INT32)(SecCoreEntryAddress - FvInfo->BaseAddress);
 
-      if (ResetVector[0] > 0x00FFFFFF) {
-        Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 32MB of the start of the FV");
+      if (EntryOffset > ARM_JUMP_OFFSET_MAX) {
+          Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset above 1MB of the start of the FV");
         return EFI_ABORTED;
       }
 
-      // Add opcode for an unconditional branch with no link. i.e.: " B SecEntryPoint"
-      ResetVector[0] |= ARMT_UNCONDITIONAL_JUMP_INSTRUCTION;
+      if ((SecCoreEntryAddress & 1) != 0) {
+        ResetVector[0] = ARM_JUMP_TO_THUMB(EntryOffset);
+      } else {
+        ResetVector[0] = ARM_JUMP_TO_ARM(EntryOffset);
+      }
 
       // SWI handler movs   pc,lr. Just in case a debugger uses SWI
-      ResetVector[2] = 0xE1B0F07E;
+      ResetVector[2] = ARM_RETURN_FROM_EXCEPTION;
 
       // Place holder to support a common interrupt handler from ROM.
       // Currently not supported. For this to be used the reset vector would not be in this FV

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