From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7A8BA20945039 for ; Wed, 5 Apr 2017 18:30:05 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP; 05 Apr 2017 18:30:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,281,1488873600"; d="scan'208";a="1151688818" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga002.fm.intel.com with ESMTP; 05 Apr 2017 18:30:04 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 5 Apr 2017 18:30:04 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 5 Apr 2017 18:30:04 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.193]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.217]) with mapi id 14.03.0319.002; Thu, 6 Apr 2017 09:30:04 +0800 From: "Wei, David" To: "Guo, Mang" , "edk2-devel@lists.01.org" CC: "Lu, ShifeiX A" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3 1/3] Fix get variable issue Thread-Index: AdKt2dOKZxtmxc2lS4mV1SfrERBh1gAm29oA Date: Thu, 6 Apr 2017 01:30:03 +0000 Message-ID: <89954A0B46707A448411A627AD4EEE3468F2416D@SHSMSX101.ccr.corp.intel.com> References: <22D2C85ED001C54AA20BFE3B0E4751D1524FCF05@SHSMSX103.ccr.corp.intel.com> In-Reply-To: <22D2C85ED001C54AA20BFE3B0E4751D1524FCF05@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch][edk2-platforms/devel-MinnowBoard3 1/3] Fix get variable issue X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 01:30:05 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: zwei4 Thanks, David Wei =20 -----Original Message----- From: Guo, Mang=20 Sent: Wednesday, April 05, 2017 2:57 PM To: edk2-devel@lists.01.org Cc: Wei, David ; Lu, ShifeiX A Subject: [Patch][edk2-platforms/devel-MinnowBoard3 1/3] Fix get variable is= sue Fix "AcpiGlobalVariable" couldn't be get issue. S3 memory info was saved in= this variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../PlatformPreMemPei/PlatformInitPreMem.c | 15 ++++++++---= ---- .../CseVariableStorageSelectorLib.c | 9 ++++++++- .../SmmCseVariableStorageSelectorLib.inf | 4 +++- .../PeiCseVariableStorageSelectorLib.c | 8 +++++++- .../PeiCseVariableStorageSelectorLib.inf | 4 +++- 5 files changed, 29 insertions(+), 11 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPr= eMemPei/PlatformInitPreMem.c b/Platform/BroxtonPlatformPkg/Common/PlatformS= ettings/PlatformPreMemPei/PlatformInitPreMem.c index a002bef..854d737 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /PlatformInitPreMem.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /PlatformInitPreMem.c @@ -907,6 +907,7 @@ PlatformInitPreMemEntryPoint ( #endif PEI_BOARD_PRE_MEM_INIT_PPI *BoardPreMemInitPpi; UINTN Instance; + UINT64 AcpiVariableSetCompatibility; =20 Status =3D (*PeiServices)->RegisterForShadow (FileHandle); =20 @@ -1070,25 +1071,25 @@ PlatformInitPreMemEntryPoint ( ASSERT_EFI_ERROR (Status); return Status; } - - VariableSize =3D sizeof (SystemConfiguration); +=20 + VariableSize =3D sizeof (AcpiVariableSetCompatibility); Status =3D VariableServices->GetVariable ( VariableServices, - PLATFORM_SETUP_VARIABLE_NAME, - &gEfiSetupVariableGuid, + ACPI_GLOBAL_VARIABLE, + &gEfiAcpiVariableCompatiblityGuid, NULL, &VariableSize, - &SystemConfiguration + &AcpiVariableSetCompatibility ); =20 AcpiVarHobSize =3D sizeof (UINT64); BuildGuidDataHob ( &gEfiAcpiVariableCompatiblityGuid, - &SystemConfiguration.AcpiVariableSetCompatibility, + &AcpiVariableSetCompatibility, sizeof (AcpiVarHobSize) ); =20 - DEBUG ((DEBUG_INFO, "AcpiVariableAddr : 0x%08x\n", SystemConfiguration= .AcpiVariableSetCompatibility)); + DEBUG ((DEBUG_INFO, "AcpiVariableAddr : 0x%08x\n", AcpiVariableSetComp= atibility));=20 =20 PERF_START_EX (NULL, "RstVctr", "IBBL", 1, 0x1000); Tick =3D CarMap->IbblPerfRecord0; diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVaria= bleStorageSelectorLib/CseVariableStorageSelectorLib.c b/Silicon/BroxtonSoC/= BroxtonSiPkg/Library/Private/DxeSmmCseVariableStorageSelectorLib/CseVariabl= eStorageSelectorLib.c index 09e6d68..1087196 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStor= ageSelectorLib/CseVariableStorageSelectorLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStor= ageSelectorLib/CseVariableStorageSelectorLib.c @@ -1,7 +1,7 @@ /** @file DXE SMM CSE Variable Storage Selector Library. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -75,6 +75,13 @@ GetCseVariableStoreFileType ( CseVari= ableFileTypePreMemoryFile : CseVari= ableFileTypePrimaryIndexFile ); + } else if ((StrCmp (VariableName, L"AcpiGlobalVariable") =3D=3D 0) && + CompareGuid (VendorGuid, &gEfiAcpiVariableCompatiblityGuid)) { + DEBUG ((EFI_D_INFO, "CseVariableStorageSelectorLib - Variable is AcpiG= lobalVariable\n")); + return (CseVariableFileInfo[CseVariableFileTypePreMemoryFile]->FileEna= bled ? + CseVari= ableFileTypePreMemoryFile : + CseVari= ableFileTypePrimaryIndexFile + ); } else { // // All other variables are stored in individual CSE files diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVaria= bleStorageSelectorLib/SmmCseVariableStorageSelectorLib.inf b/Silicon/Broxto= nSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStorageSelectorLib/SmmCs= eVariableStorageSelectorLib.inf index 5956383..bbbde90 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStor= ageSelectorLib/SmmCseVariableStorageSelectorLib.inf +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/DxeSmmCseVariableStor= ageSelectorLib/SmmCseVariableStorageSelectorLib.inf @@ -4,7 +4,7 @@ # Determines which CSE resources to consume in SMM. # Example: HECI1 or HECI2. # -# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -37,6 +37,7 @@ MdePkg/MdePkg.dec BroxtonSiPkg/BroxtonSiPkg.dec BroxtonSiPkg/BroxtonSiPrivate.dec + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec =20 [Protocols] gEfiHeciSmmProtocolGuid @@ -52,3 +53,4 @@ [Guids] gEfiMemoryConfigVariableGuid gEfiSetupVariableGuid + gEfiAcpiVariableCompatiblityGuid diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariable= StorageSelectorLib/PeiCseVariableStorageSelectorLib.c b/Silicon/BroxtonSoC/= BroxtonSiPkg/Library/Private/PeiCseVariableStorageSelectorLib/PeiCseVariabl= eStorageSelectorLib.c index cee10ea..a9d93fe 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorage= SelectorLib/PeiCseVariableStorageSelectorLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorage= SelectorLib/PeiCseVariableStorageSelectorLib.c @@ -1,7 +1,7 @@ /** @file PEI CSE Variable Storage Selector Library. =20 - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -73,6 +73,12 @@ GetCseVariableStoreFileType ( CseVari= ableFileTypePreMemoryFile : CseVari= ableFileTypePrimaryIndexFile ); +} else if ((StrCmp (VariableName, L"AcpiGlobalVariable") =3D=3D 0) && + CompareGuid (VendorGuid, &gEfiAcpiVariableCompatiblityGuid)) { + return (CseVariableFileInfo[CseVariableFileTypePreMemoryFile]->FileEna= bled ? + CseVari= ableFileTypePreMemoryFile : + CseVari= ableFileTypePrimaryIndexFile + ); } else { // // All other variables are stored in individual CSE files diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariable= StorageSelectorLib/PeiCseVariableStorageSelectorLib.inf b/Silicon/BroxtonSo= C/BroxtonSiPkg/Library/Private/PeiCseVariableStorageSelectorLib/PeiCseVaria= bleStorageSelectorLib.inf index bd6cce0..474a9b7 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorage= SelectorLib/PeiCseVariableStorageSelectorLib.inf +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/Private/PeiCseVariableStorage= SelectorLib/PeiCseVariableStorageSelectorLib.inf @@ -4,7 +4,7 @@ # Determines which CSE resources to consume in PEI. # Example: HECI1 or HECI2. # -# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -35,6 +35,7 @@ MdePkg/MdePkg.dec BroxtonSiPkg/BroxtonSiPkg.dec BroxtonSiPkg/BroxtonSiPrivate.dec + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec =20 [LibraryClasses] BaseLib @@ -45,3 +46,4 @@ [Guids] gEfiMemoryConfigVariableGuid gEfiSetupVariableGuid + gEfiAcpiVariableCompatiblityGuid --=20 2.10.1.windows.1