From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F51220080F1B for ; Wed, 12 Apr 2017 01:14:16 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2017 01:14:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,189,1488873600"; d="scan'208";a="86422823" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga005.jf.intel.com with ESMTP; 12 Apr 2017 01:14:15 -0700 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 12 Apr 2017 01:14:15 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 12 Apr 2017 01:14:14 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.193]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0319.002; Wed, 12 Apr 2017 16:14:13 +0800 From: "Wei, David" To: "Guo, Mang" , "edk2-devel@lists.01.org" CC: "Lu, ShifeiX A" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3] Fix S3 resume failure Thread-Index: AdKzWUszpoIGoux4S/SSr4rw7zutDwAC127w Date: Wed, 12 Apr 2017 08:14:12 +0000 Message-ID: <89954A0B46707A448411A627AD4EEE3468F265AC@SHSMSX101.ccr.corp.intel.com> References: <22D2C85ED001C54AA20BFE3B0E4751D152501751@SHSMSX103.ccr.corp.intel.com> In-Reply-To: <22D2C85ED001C54AA20BFE3B0E4751D152501751@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch][edk2-platforms/devel-MinnowBoard3] Fix S3 resume failure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Apr 2017 08:14:16 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: zwei4 =20 Thanks, David Wei =20 -----Original Message----- From: Guo, Mang=20 Sent: Wednesday, April 12, 2017 2:52 PM To: edk2-devel@lists.01.org Cc: Wei, David ; Lu, ShifeiX A Subject: [Patch][edk2-platforms/devel-MinnowBoard3] Fix S3 resume failure When restoring MSR for S3 setting, SmmStartupThisAp will return error if CP= U index is BSP. This issue caused S3 resume failed sometimes. This patch is= mainly fix this issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang --- .../PlatformDsc/PcdsFeatureFlag.dsc | 7 ++++++- .../Cpu/PowerManagement/Smm/PowerMgmtS3.c | 23 ++++++++++++------= ---- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/PcdsFeatureFlag.dsc b/= Platform/BroxtonPlatformPkg/PlatformDsc/PcdsFeatureFlag.dsc index 6762a41..19e27ad 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/PcdsFeatureFlag.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/PcdsFeatureFlag.dsc @@ -1,7 +1,7 @@ ## @file # Platform Feature Pcd Description. # -# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -91,3 +91,8 @@ # new core to see if we can re-enable this gPlatformModuleTokenSpaceGuid.PcdDeprecatedFunctionRemove|FALSE =20 + ## Indicates if SMM Startup AP in a blocking fashion. + # TRUE - SMM Startup AP in a blocking fashion.
+ # FALSE - SMM Startup AP in a non-blocking fashion.
+ # @Prompt SMM Startup AP in a blocking fashion. + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE \ No newline at end of file diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerM= gmtS3.c b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmt= S3.c index 4385320..eb36343 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmtS3.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/PowerManagement/Smm/PowerMgmtS3.c @@ -1,7 +1,7 @@ /** @file This is the SMM driver for saving and restoring the powermanagement rela= ted MSRs. =20 - Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -140,15 +140,18 @@ RunOnAllLogicalProcessors ( // Run the procedure on all logical processors. // (*Procedure) (Buffer); - for (Index =3D 1; Index < gSmst->NumberOfCpus; Index++) { - Status =3D EFI_NOT_READY; - while (Status !=3D EFI_SUCCESS) { - Status =3D gSmst->SmmStartupThisAp (Procedure, Index, Buffer); - if (Status !=3D EFI_SUCCESS) { - // - // SmmStartupThisAp might return failure if AP is busy executing s= ome other code. Let's wait for sometime and try again. - // - MicroSecondDelay (PPM_WAIT_PERIOD); + for (Index =3D 0; Index < gSmst->NumberOfCpus; Index++) { + if (Index !=3D gSmst->CurrentlyExecutingCpu) { + Status =3D EFI_NOT_READY; + while (Status !=3D EFI_SUCCESS) { + Status =3D gSmst->SmmStartupThisAp (Procedure, Index, Buffer); + ASSERT(Status !=3D EFI_INVALID_PARAMETER); + if (Status !=3D EFI_SUCCESS) { + // + // SmmStartupThisAp might return failure if AP is busy executing= some other code. Let's wait for sometime and try again. + // + MicroSecondDelay (PPM_WAIT_PERIOD); + } } } } --=20 2.10.1.windows.1