From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 397A82194EB56 for ; Thu, 13 Apr 2017 02:22:02 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Apr 2017 02:22:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,194,1488873600"; d="scan'208";a="248159667" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga004.fm.intel.com with ESMTP; 13 Apr 2017 02:22:01 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 13 Apr 2017 02:22:01 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.193]) by shsmsx102.ccr.corp.intel.com ([169.254.2.246]) with mapi id 14.03.0319.002; Thu, 13 Apr 2017 17:21:57 +0800 From: "Wei, David" To: "Lu, ShifeiX A" , "edk2-devel@lists.01.org" CC: "Wei, David" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3] GPIO clean up. Thread-Index: AQHStDc1WoPZuRt3o0yihCS3Q4AvgKHDBj2A Date: Thu, 13 Apr 2017 09:21:56 +0000 Message-ID: <89954A0B46707A448411A627AD4EEE3468F26EB9@SHSMSX101.ccr.corp.intel.com> References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch][edk2-platforms/devel-MinnowBoard3] GPIO clean up. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 13 Apr 2017 09:22:02 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: zwei4 Thanks, David Wei =20 -----Original Message----- From: Lu, ShifeiX A=20 Sent: Thursday, April 13, 2017 5:20 PM To: edk2-devel@lists.01.org Cc: Wei, David Subject: [Patch][edk2-platforms/devel-MinnowBoard3] GPIO clean up. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex --- .../MinnowBoard3/BoardInitPostMem/BoardGpios.c | 12 +- .../MinnowBoard3/BoardInitPostMem/BoardGpios.h | 216 +++++++----------= ---- 2 files changed, 69 insertions(+), 159 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardGpios.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPo= stMem/BoardGpios.c index 5d27656..7e7c327 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Gpios.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Gpios.c @@ -1,7 +1,7 @@ /** @file Gpio setting for multiplatform. =20 - Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -188,10 +188,6 @@ MultiPlatformGpioProgram ( GpioPadConfigTable (sizeof (mBXT_GpioInitData_NW) / sizeof (mBXT_Gpi= oInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW); GpioPadConfigTable (sizeof (mBXT_GpioInitData_W) / sizeof (mBXT_Gpio= InitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W); GpioPadConfigTable (sizeof (mBXT_GpioInitData_SW) / sizeof (mBXT_Gpi= oInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW); - GpioPadConfigTable (sizeof (mBXT_GpioInitData_N_LH) / sizeof (mBXT_G= pioInitData_N_LH[0]), mBXT_GpioInitData_N_LH); - GpioPadConfigTable (sizeof (mBXT_GpioInitData_SW_LH) / sizeof (mBXT_= GpioInitData_SW_LH[0]), mBXT_GpioInitData_SW_LH); - GpioPadConfigTable (sizeof (mBXT_GpioInitData_W_LH) / sizeof (mBXT_G= pioInitData_W_LH[0]), mBXT_GpioInitData_W_LH); - GpioPadConfigTable (sizeof (mBXT_GpioInitData_NW_LH) / sizeof (mBXT_= GpioInitData_NW_LH[0]), mBXT_GpioInitData_NW_LH); =20 if (SystemConfiguration.ScIshEnabled =3D=3D 0) { DEBUG ((DEBUG_INFO, "Switch ISH_I2C0 & ISH_I2C1 to LPSS_I2C5 and L= PSS I2C6. \n" )); @@ -262,9 +258,9 @@ MultiPlatformGpioProgram ( // DEBUG ((DEBUG_INFO, "Dump Community pad registers, Board ID: 0x%X\n"= , PlatformInfoHob->BoardId)); DumpGpioPadTable (sizeof (mBXT_GpioInitData_N) / sizeof (mBXT_GpioIn= itData_N[0]), PlatformInfoHob->PlatformGpioSetting_N); - DumpGpioPadTable (sizeof (mBXT_GpioInitData_NW_LH) / sizeof (mBXT_Gp= ioInitData_NW_LH[0]), PlatformInfoHob->PlatformGpioSetting_NW); - DumpGpioPadTable (sizeof (mBXT_GpioInitData_W_LH) / sizeof (mBXT_Gpi= oInitData_W_LH[0]), PlatformInfoHob->PlatformGpioSetting_W); - DumpGpioPadTable (sizeof (mBXT_GpioInitData_SW_LH) / sizeof (mBXT_Gp= ioInitData_SW_LH[0]), PlatformInfoHob->PlatformGpioSetting_SW); + DumpGpioPadTable (sizeof (mBXT_GpioInitData_NW) / sizeof (mBXT_GpioI= nitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW); + DumpGpioPadTable (sizeof (mBXT_GpioInitData_W) / sizeof (mBXT_GpioIn= itData_W[0]), PlatformInfoHob->PlatformGpioSetting_W); + DumpGpioPadTable (sizeof (mBXT_GpioInitData_SW) / sizeof (mBXT_GpioI= nitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW); break; default: // diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPo= stMem/BoardGpios.h index 6bc1619..0928e16 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Gpios.h +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Gpios.h @@ -1,7 +1,7 @@ /** @file GPIO setting for Broxton. =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -72,16 +72,20 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_N[] =3D BXT_GPIO_PAD_CONF(L"GPIO_6", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0030, NORTH),//Mux with DISP1_RST_N based on the SW3= switch BXT_GPIO_PAD_CONF(L"GPIO_7", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0038, NORTH),//Mux with DISP1_TOUCH_INT_N based on t= he SW3 switch BXT_GPIO_PAD_CONF(L"GPIO_8", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0040, NORTH),//Mux with DISP1_TOUCH_RST_N based on t= he SW3 switch - BXT_GPIO_PAD_CONF(L"GPIO_9", M0 , GPI , NA ,= NA , Level , Wake_Disabled, P_20K_L, Inverted,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0048, NORTH),//Feature:Interrupt Net in= Sch: SPI_TPM_HDR_IRQ_N - BXT_GPIO_PAD_CONF(L"GPIO_10", M0 , GPI , NA ,= NA , Level , Wake_Enabled , P_20K_L, Inverted,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0050, NORTH),//Feature:WAKE Net in= Sch: SLTA_SDIO_WAKE_N - BXT_GPIO_PAD_CONF(L"GPIO_11", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_L, Inverted, SCI, TxDRxE , = NA, GPIO_PADBAR+0x0058, NORTH),//Feature:Runtime SCI Net in= Sch: SOC_RUNTIME_SCI_N - BXT_GPIO_PAD_CONF(L"GPIO_12", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_L, Inverted, SCI, TxDRxE , = NA, GPIO_PADBAR+0x0060, NORTH),//Feature:Wake SCI Net in= Sch: EC_WAKE_SCI_N - BXT_GPIO_PAD_CONF(L"GPIO_14", M0 , GPI , GPIO_D,= NA , Edge , Wake_Disabled, P_20K_L, Inverted,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0070, NORTH),//Feature:Interrupt Net in= Sch: FGR_INT + BXT_GPIO_PAD_CONF(L"GPIO_9", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0048, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_10", M0 , GPI , NA ,= NA , Level , Wake_Enabled , P_20K_L, Inverted,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0050, NORTH),//Feature: LB =20 + BXT_GPIO_PAD_CONF(L"GPIO_11", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0058, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_12", M1 , NA , NA ,= NA , NA , Wake_Enabled , P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0060, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_13", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0068, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0070, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0078, NORTH),//Feature: LB BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,D= isPuPd, GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in= Sch: SIM_CON_CD1, falling edge trigger - BXT_GPIO_PAD_CONF(L"GPIO_18", M0 , GPI , NA ,= NA , Level , Wake_Disabled, P_20K_H, Inverted ,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0090, NORTH),//Feature:Interrupt Net in= Sch: TCHPAD_INT_N - BXT_GPIO_PAD_CONF(L"GPIO_20", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_L, NA ,IOAPIC, TxDRxE, = NA, GPIO_PADBAR+0x00A0, NORTH),//Feature:Interrupt Net in= Sch: NFC_IRQ_CONN - BXT_GPIO_PAD_CONF(L"GPIO_21", M0 , GPI , NA ,= NA , Level , Wake_Disabled, P_20K_H, Inverted,IOAPIC, TxDRxE, = NA, GPIO_PADBAR+0x00A8, NORTH),//Feature:Interrupt Net in= Sch: TCH_PNL_INTR_LS_N - BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPI , GPIO_D,= NA , Level , Wake_Disabled, P_20K_L,Inverted , NA, NA , = NA, GPIO_PADBAR+0x00B8, NORTH),//Feature:Present Pin Net in= Sch: SATA_ODD_PRSNT_N + BXT_GPIO_PAD_CONF(L"GPIO_17", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0088, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0090, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0098, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00A0, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00A8, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO , NA , = HI , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00B8, NORTH),//Feature: LB USB Power in LFH BXT_GPIO_PAD_CONF(L"GPIO_24", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0 BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPI , ACPI_D,= NA , Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , = NA, GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in= Sch: SATA_ODD_DA_IN BXT_GPIO_PAD_CONF(L"GPIO_26", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN @@ -89,12 +93,12 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_N[] =3D BXT_GPIO_PAD_CONF(L"GPIO_28", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00E0, NORTH),// Net in= Sch: ISH_GPIO10 BXT_GPIO_PAD_CONF(L"GPIO_29", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00E8, NORTH),// Net in= Sch: ISH_GPIO11 BXT_GPIO_PAD_CONF(L"GPIO_30", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00F0, NORTH),// Net in= Sch: ISH_GPIO12 - BXT_GPIO_PAD_CONF(L"GPIO_31", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00F8, NORTH),// Net in= Sch: SUSCLK1 + BXT_GPIO_PAD_CONF(L"GPIO_31", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00F8, NORTH),//Feature: SUSCLK1 BXT_GPIO_PAD_CONF(L"GPIO_32", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0100, NORTH),// Net in= Sch: SUSCLK2 - BXT_GPIO_PAD_CONF(L"GPIO_33", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0108, NORTH),// Net in= Sch: ISH_GPIO15, SUSCLK3 - BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0110, NORTH),//Feature:Power Enable Net in= Sch: USB2_CAM_PWR_EN + BXT_GPIO_PAD_CONF(L"GPIO_33", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0108, NORTH),//Feature: SUSCLK3 + BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0110, NORTH),//Feature: PWM BXT_GPIO_PAD_CONF(L"GPIO_35 PWM1", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_5K_H , NA , NA, NA , = NA, GPIO_PADBAR+0x0118, NORTH),//Feature:Power Enable Net in= Sch: TCH_PNL_PG - BXT_GPIO_PAD_CONF(L"GPIO_36 PWM2", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_5K_H , NA , NA, NA , = NA, GPIO_PADBAR+0x0120, NORTH),//Feature:Reset Net in= Sch: TCH_PNL_RST_LS_N + BXT_GPIO_PAD_CONF(L"GPIO_36 PWM2", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0120, NORTH),//Feature: PWM BXT_GPIO_PAD_CONF(L"GPIO_38 LPSS_UART0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,D= isPuPd, GPIO_PADBAR+0x0130, NORTH), BXT_GPIO_PAD_CONF(L"GPIO_39 LPSS_UART0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,D= isPuPd, GPIO_PADBAR+0x0138, NORTH), BXT_GPIO_PAD_CONF(L"GPIO_40 LPSS_UART0_RTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,D= isPuPd, GPIO_PADBAR+0x0140, NORTH), @@ -104,7 +108,7 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_N[] =3D BXT_GPIO_PAD_CONF(L"GPIO_44 LPSS_UART1_RTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,D= isPuPd, GPIO_PADBAR+0x0160, NORTH), BXT_GPIO_PAD_CONF(L"GPIO_45 LPSS_UART1_CTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_NONE , NA , NA, HizRx0I,D= isPuPd, GPIO_PADBAR+0x0168, NORTH), BXT_GPIO_PAD_CONF(L"GPIO_48 LPSS_UART2_RTS_B", M0 , GPI , GPIO_D,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0180, NORTH),//Not used on RVP - BXT_GPIO_PAD_CONF(L"GPIO_49 LPSS_UART2_CTS_B", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_H,Inverted , SMI, NA , = NA, GPIO_PADBAR+0x0188, NORTH),//Feature:SOC_EXTSMI_N Net in= Sch: SOC_EXTSMI_N + BXT_GPIO_PAD_CONF(L"GPIO_49 LPSS_UART2_CTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0188, NORTH),//Feature: LPSS_UART1 BXT_GPIO_PAD_CONF(L"GPIO_62 GP_CAMERASB00", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x0190, NORTH),//CAM_FLASH_RST_N BXT_GPIO_PAD_CONF(L"GPIO_63 GP_CAMERASB01", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x0198, NORTH),//CAM_FLASH_TORCH BXT_GPIO_PAD_CONF(L"GPIO_64 GP_CAMERASB02", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01A0, NORTH),//CAM_FLASH_TRIG @@ -177,21 +181,21 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_NW [] =3D BXT_GPIO_PAD_CONF(L"PROCHOT_B", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I , = SAME, GPIO_PADBAR+0x00F8, NORTHWEST), BXT_GPIO_PAD_CONF(L"PMIC_I2C_SCL", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_1K_H , NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0100, NORTHWEST), BXT_GPIO_PAD_CONF(L"PMIC_I2C_SDA", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_1K_H , NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0108, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_74 AVS_I2S1_MCLK", M0 , GPO ,GPIO_D, = LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0110, NORTHWEST),//Feature:SOC_CS_WAKE Net i= n Sch:SOC_CS_WAKE - BXT_GPIO_PAD_CONF(L"GPIO_75 AVS_I2S1_BCLK", M0 , GPI ,GPIO_D, = NA , Level ,Wake_Disabled, P_20K_L, Inverted,IOAPIC ,TxDRxE , = NA, GPIO_PADBAR+0x0118, NORTHWEST),//Feature:Wake Net i= n Sch:NGFF_CONN_UART_WAKE_N - BXT_GPIO_PAD_CONF(L"GPIO_76 AVS_I2S1_WS_SYNC", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0120, NORTHWEST),//Feature:Wake Net i= n Sch:GNSS_UART_WAKE_N - BXT_GPIO_PAD_CONF(L"GPIO_77 AVS_I2S1_SDI", M0 , GPO ,GPIO_D, = LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0128, NORTHWEST),//Feature:Reset Net i= n Sch:MIPI_DSI_RST_1_8V - BXT_GPIO_PAD_CONF(L"GPIO_78 AVS_I2S1_SDO", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I ,D= isPuPd, GPIO_PADBAR+0x0130, NORTHWEST),//Feature:Power enable Net i= n Sch:USB2_WWAN_PWR_EN - BXT_GPIO_PAD_CONF(L"GPIO_79 AVS_M_CLK_A1", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0138, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_80 AVS_M_CLK_B1", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0140, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_81 AVS_M_DATA_1", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , = EnPd, GPIO_PADBAR+0x0148, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_82 AVS_M_CLK_AB2", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0150, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_74 AVS_I2S1_MCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0110, NORTHWEST),//Feature:AVS_I2S1_MCLK + BXT_GPIO_PAD_CONF(L"GPIO_75 AVS_I2S1_BCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0118, NORTHWEST),//Feature:AVS_I2S1_BCLK + BXT_GPIO_PAD_CONF(L"GPIO_76 AVS_I2S1_WS_SYNC", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0120, NORTHWEST),//Feature:Wake + BXT_GPIO_PAD_CONF(L"GPIO_77 AVS_I2S1_SDI", M0 , GPI , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0128, NORTHWEST),//Feature:LPE Hdr + BXT_GPIO_PAD_CONF(L"GPIO_78 AVS_I2S1_SDO", M0 , GPI , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0130, NORTHWEST),//Feature:LPE Hdr + BXT_GPIO_PAD_CONF(L"GPIO_79 AVS_M_CLK_A1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0138, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_80 AVS_M_CLK_B1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0140, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_81 AVS_M_DATA_1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,TxDRxE , = EnPd, GPIO_PADBAR+0x0148, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_82 AVS_M_CLK_AB2", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0150, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_83 AVS_M_DATA_2", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , = EnPd, GPIO_PADBAR+0x0158, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK", M2 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0160, NORTHWEST),//Spare signal, set to GPI. Net i= n Sch:HDA_RSTB - BXT_GPIO_PAD_CONF(L"GPIO_85 AVS_I2S2_BCLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0168, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_86 AVS_I2S2_WS_SYNC", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0170, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_87 AVS_I2S2_SDI", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , = EnPd, GPIO_PADBAR+0x0178, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_88 AVS_I2S2_SDO", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0180, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0160, NORTHWEST),//Spare signal, set to GPI. Net i= n Sch:HDA_RSTB + BXT_GPIO_PAD_CONF(L"GPIO_85 AVS_I2S2_BCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0168, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_86 AVS_I2S2_WS_SYNC", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0170, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_87 AVS_I2S2_SDI", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0178, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_88 AVS_I2S2_SDO", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0180, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_89 AVS_I2S3_BCLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0188, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_90 AVS_I2S3_WS_SYNC", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0190, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_91 AVS_I2S3_SDI", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , = EnPd, GPIO_PADBAR+0x0198, NORTHWEST), @@ -204,22 +208,27 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_NW [] =3D BXT_GPIO_PAD_CONF(L"GPIO_102 FST_SPI_IO3", M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01D0, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_103 FST_SPI_CLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01D8, NORTHWEST), BXT_GPIO_PAD_CONF(L"FST_SPI_CLK_FB", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_NONE , NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01E0, NORTHWEST),//no pin out - BXT_GPIO_PAD_CONF(L"GPIO_104 GP_SSP_0_CLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x01E8, NORTHWEST),//no pin out - BXT_GPIO_PAD_CONF(L"GPIO_105 GP_SSP_0_FS0", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x01F0, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I ,D= isPuPd, GPIO_PADBAR+0x01F8, NORTHWEST),//GP_SSP_0_FS1 - BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I , = SAME, GPIO_PADBAR+0x0200, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0208, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_104 GP_SSP_0_CLK", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01E8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_105 GP_SSP_0_FS0", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01F0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01F8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x0200, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x0208, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , GPI ,GPIO_D, = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP - BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0218, NORTHWEST),//Feature: Reset Net = in Sch: FGR_RESET_N + BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0218, NORTHWEST),//Feature: LPSS UART Hdr BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M0 , GPI ,GPIO_D, = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0220, NORTHWEST),//Not used on RVP - BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M0 , GPI , NA , = NA , Level ,Wake_Disabled, P_20K_L, NA ,IOAPIC ,TxDRxE , = NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: Interrput Net = in Sch: SOC_CODEC_IRQ - BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: Reset Net = in Sch: NGFF_MODEM_RESET_N - BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0238, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0240, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0248, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0250, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I , = SAME, GPIO_PADBAR+0x0258, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0260, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr + BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr + BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0238, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0240, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0248, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0250, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0258, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0260, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA + BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL + BXT_GPIO_PAD_CONF(L"GPIO_196 PANEL1_VDDEN", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0048, NORTHWEST),//DISP1_VDDEN + BXT_GPIO_PAD_CONF(L"GPIO_197 PANEL1_BKLTEN", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0050, NORTHWEST),//DISP1_BKLTEN + BXT_GPIO_PAD_CONF(L"GPIO_198 PANEL1_BKLTCTL", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0058, NORTHWEST),//DISP1_BLTCTL }; =20 // @@ -242,15 +251,20 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_W [] =3D BXT_GPIO_PAD_CONF(L"GPIO_133 LPSS_I2C4_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0048, WEST), BXT_GPIO_PAD_CONF(L"GPIO_138 LPSS_I2C7_SDA", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D0RxDRx0I, = EnPu, GPIO_PADBAR+0x0070, WEST),// RFKILL_N BXT_GPIO_PAD_CONF(L"GPIO_139 LPSS_I2C7_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D0RxDRx0I, = EnPu, GPIO_PADBAR+0x0078, WEST),//HALL_STATE - BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0090, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0098, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_150 ISH_GPIO_4", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A0, WEST),//Feature: Reset Net in= Sch: NFC_RESET_N + BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0090, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0098, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_150 ISH_GPIO_4", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A0, WEST),//Feature: AVS_I2S5_BCLK BXT_GPIO_PAD_CONF(L"GPIO_151 ISH_GPIO_5", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A8, WEST),//Feature: RF_KILL_WWAN Net in= Sch: NGFF_WWAN_RF_KILL_1P8_N + BXT_GPIO_PAD_CONF(L"GPIO_152 ISH_GPIO_6", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00B0, WEST),//Feature: AVS_I2S5_SDI BXT_GPIO_PAD_CONF(L"GPIO_153 ISH_GPIO_7", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00B8, WEST), BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00C0, WEST),//Feature: BT_Disable Net in= Sch: BT_DISABLE2_1P8_N BXT_GPIO_PAD_CONF(L"GPIO_155 ISH_GPIO_9", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00C8, WEST),//CG2000 PDB: If PDB =3D 0: power-down; = If PDB =3D 1: power-up, it is the same in ISH/LPSS mode + BXT_GPIO_PAD_CONF(L"GPIO_209 PCIE_CLKREQ0_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00D0, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00D8, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_211 PCIE_CLKREQ2_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00E0, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_212 PCIE_CLKREQ3_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00E8, WEST), BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_0", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00F0, WEST), BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_1", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00F8, WEST), BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_2", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x0100, WEST), @@ -304,12 +318,12 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_SW[]=3D BXT_GPIO_PAD_CONF(L"GPIO_174 SDCARD_D1", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x00B8 , SOUTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_175 SDCARD_D2", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x00C0 , SOUTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_176 SDCARD_D3", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x00C8 , SOUTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_177 SDCARD_CD_B", M0, GPI , GPIO_D = , NA , Edge ,Wake_Disabled, P_20K_H, NA , NA ,TxDRxE = ,NA ,GPIO_PADBAR+0x00D0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_177 SDCARD_CD_B", M0, GPI , GPIO_D = , NA , Edge ,Wake_Disabled, P_NONE, NA , NA ,TxDRxE = , NA, GPIO_PADBAR+ 0x00D0 , SOUTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_178 SDCARD_CMD", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,DisPuPd,GPIO_PADBAR+0x00D8 , SOUTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_186 SDCARD_LVL_WP", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Valu= e,SAME ,GPIO_PADBAR+0x00E0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_186 SDCARD_LVL_WP", M0, GPI , GPIO_D = , NA , Edge ,Wake_Disabled, P_20K_L,Inverted , NA ,Last_Valu= e, SAME,GPIO_PADBAR+0x00E0 , SOUTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_182 EMMC0_STROBE", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I = ,SAME ,GPIO_PADBAR+0x00E8 , SOUTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_183 SDIO_PWR_DOWN_B", M0, GPO , GPIO_D = , LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA = ,NA ,GPIO_PADBAR+0x00F0 , SOUTHWEST),// Feature:Power Enable Net in = Sch:SD_CARD_PWR_EN_N - BXT_GPIO_PAD_CONF(L"SMB_ALERTB", M0, GPI , GPIO_D = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d,SAME ,GPIO_PADBAR+0x00F8 , SOUTHWEST),//not used on RVP + BXT_GPIO_PAD_CONF(L"SMB_ALERTB", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d, SAME, GPIO_PADBAR+ 0x00F8 , SOUTHWEST),//Feature: SMB_ALERTB }; =20 BXT_GPIO_PAD_INIT mBXT_GpioInitData_Audio_SSP6 []=3D @@ -347,106 +361,6 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_EPI_Override[] = =3D BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M0, GPO, GPIO_D,L= O, NA, Wake_Disabled,P_20K_L, NA, NA, NA, = NA, GPIO_PADBAR + 0x0020, NORTHWEST),//Feature: SD_I2C MUX SEL = Net in Sch: INA_MUX_SEL }; =20 -// -// North West Community -// -BXT_GPIO_PAD_INIT mBXT_GpioInitData_NW_LH []=3D -{ - // - // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, IO= STerm, MMIO_Offset, Community - // - BXT_GPIO_PAD_CONF(L"GPIO_74 AVS_I2S1_MCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0110, NORTHWEST),//Feature:AVS_I2S1_MCLK - BXT_GPIO_PAD_CONF(L"GPIO_75 AVS_I2S1_BCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0118, NORTHWEST),//Feature:AVS_I2S1_BCLK - BXT_GPIO_PAD_CONF(L"GPIO_77 AVS_I2S1_SDI", M0 , GPI , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0128, NORTHWEST),//Feature:LPE Hdr - BXT_GPIO_PAD_CONF(L"GPIO_78 AVS_I2S1_SDO", M0 , GPI , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0130, NORTHWEST),//Feature:LPE Hdr - BXT_GPIO_PAD_CONF(L"GPIO_79 AVS_M_CLK_A1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0138, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_80 AVS_M_CLK_B1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0140, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_81 AVS_M_DATA_1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,TxDRxE , = EnPd, GPIO_PADBAR+0x0148, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_82 AVS_M_CLK_AB2", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0150, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_104 GP_SSP_0_CLK", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01E8, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_105 GP_SSP_0_FS0", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01F0, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01F8, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x0200, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x0208, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0218, NORTHWEST),//Feature: LPSS UART Hdr - BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr - BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr - BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA - BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL - BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0238, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0240, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0248, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0250, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0258, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0260, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_196 PANEL1_VDDEN", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0048, NORTHWEST),//DISP1_VDDEN - BXT_GPIO_PAD_CONF(L"GPIO_197 PANEL1_BKLTEN", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0050, NORTHWEST),//DISP1_BKLTEN - BXT_GPIO_PAD_CONF(L"GPIO_198 PANEL1_BKLTCTL", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0058, NORTHWEST),//DISP1_BLTCTL - BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0160, NORTHWEST),//Spare signal, set to GPI. Net i= n Sch:HDA_RSTB - BXT_GPIO_PAD_CONF(L"GPIO_85 AVS_I2S2_BCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0168, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_86 AVS_I2S2_WS_SYNC", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0170, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_87 AVS_I2S2_SDI", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0178, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_88 AVS_I2S2_SDO", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0180, NORTHWEST), -}; - - -BXT_GPIO_PAD_INIT mBXT_GpioInitData_N_LH[] =3D -{ - // - // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, = IOSTerm,MMIO_Offset,Community - // - BXT_GPIO_PAD_CONF(L"GPIO_9", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0048, NORTH),//Feature:LB - BXT_GPIO_PAD_CONF(L"GPIO_11", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0058, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_12", M1 , NA , NA ,= NA , NA , Wake_Enabled , P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0060, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_13", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0068, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0070, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0078, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_17", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0088, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0090, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0098, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00A0, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00A8, NORTH),//Feature: LB - BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO , NA , = HI , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00B8, NORTH),//Feature: LB USB Power in LFH - BXT_GPIO_PAD_CONF(L"GPIO_31", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00F8, NORTH),//Feature: SUSCLK1 - BXT_GPIO_PAD_CONF(L"GPIO_33", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0108, NORTH),//Feature: SUSCLK3 - BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0110, NORTH),//Feature: PWM - BXT_GPIO_PAD_CONF(L"GPIO_36 PWM2", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0120, NORTH),//Feature: PWM - BXT_GPIO_PAD_CONF(L"GPIO_49 LPSS_UART2_CTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0188, NORTH),//Feature: LPSS_UART1 -}; - -// -// West Community -// -BXT_GPIO_PAD_INIT mBXT_GpioInitData_W_LH [] =3D -{ - // - // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,= GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L, Inverted,GPI_ROUT,IOSstae, IO= STerm, MMIO_Offset, Community - // - BXT_GPIO_PAD_CONF(L"GPIO_150 ISH_GPIO_4", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A0, WEST),//Feature: AVS_I2S5_BCLK - BXT_GPIO_PAD_CONF(L"GPIO_152 ISH_GPIO_6", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+ 0x00B0, WEST),//Feature: AVS_I2S5_SDI - BXT_GPIO_PAD_CONF(L"GPIO_209 PCIE_CLKREQ0_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00D0, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00D8, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_211 PCIE_CLKREQ2_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00E0, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_212 PCIE_CLKREQ3_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00E8, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0090, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0098, WEST), -}; - - // - // South West Community - // -BXT_GPIO_PAD_INIT mBXT_GpioInitData_SW_LH []=3D -{ - // - // Group Pin#: pad_name, PMode,GPIO_Config,HostS= w,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, I= OSTerm,MMIO_Offset, Community - // - BXT_GPIO_PAD_CONF(L"GPIO_177 SDCARD_CD_B", M0, GPI , GPIO_D = , NA , Edge ,Wake_Disabled, P_NONE, NA , NA ,TxDRxE = , NA, GPIO_PADBAR+ 0x00D0 , SOUTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_186 SDCARD_LVL_WP", M0, GPI , GPIO_D = , NA , Edge ,Wake_Disabled, P_20K_L,Inverted , NA ,Last_Valu= e, SAME,GPIO_PADBAR+ 0x00E0 , SOUTHWEST), - BXT_GPIO_PAD_CONF(L"SMB_ALERTB", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d, SAME, GPIO_PADBAR+ 0x00F8 , SOUTHWEST),//Feature: SMB_ALERTB -}; - BXT_GPIO_PAD_INIT mBXT_GpioInitData_LPSS_I2C[] =3D { BXT_GPIO_PAD_CONF(L"GPIO_134 LPSS_I2C5_SDA", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, = EnPd, GPIO_PADBAR+0x0050, WEST), --=20 2.7.0.windows.1