From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=david.wei@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DD4FD2034BBF5 for ; Tue, 14 Nov 2017 21:16:25 -0800 (PST) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Nov 2017 21:20:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,398,1505804400"; d="scan'208";a="175923008" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga005.fm.intel.com with ESMTP; 14 Nov 2017 21:20:33 -0800 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 14 Nov 2017 21:20:33 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 14 Nov 2017 21:20:33 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.159]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.218]) with mapi id 14.03.0319.002; Wed, 15 Nov 2017 13:19:53 +0800 From: "Wei, David" To: "Rytkonen, Teemu S" , "edk2-devel@lists.01.org" CC: "Ryu, Misun" , "Loeppert, Anthony" , "Jones, Mark L" , "Guo, Mang" , "Wei, David" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] BensonGlacier: Enable generic SPI device Thread-Index: AQHTXWxLeWa497GRDEyz+mmWJY0NmqMU56jw Date: Wed, 15 Nov 2017 05:19:52 +0000 Message-ID: <89954A0B46707A448411A627AD4EEE3468FBB682@SHSMSX101.ccr.corp.intel.com> References: <20171114171605.6844-1-teemu.s.rytkonen@intel.com> In-Reply-To: <20171114171605.6844-1-teemu.s.rytkonen@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWFlNTdhNGEtZjU3My00YzU5LWFlNzQtN2ZkMGRjOGMxNGQzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJ5K1BHU1wvcTNoUlFQcTVOSnMzSFBvWnk3ZmVEOGFzWWJQZFdCNUhJYmdJZDJMNFg0RmlmUWRxOUh0aHlwaGNzTSJ9 x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] BensonGlacier: Enable generic SPI device X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Nov 2017 05:16:26 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: zwei4 Thanks, David Wei Intel SSG/STO/UEFI BIOS =20 > -----Original Message----- > From: Rytkonen, Teemu S > Sent: Wednesday, November 15, 2017 1:16 AM > To: edk2-devel@lists.01.org > Cc: Ryu, Misun ; Loeppert, Anthony > ; Jones, Mark L ; > Wei, David ; Guo, Mang > Subject: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] > BensonGlacier: Enable generic SPI device >=20 > -Enable generic SPI device for BensonGlacier config to be > used with SenseHat board. > -Enable GPIO config to enable SenseHat board programming >=20 > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Teemu Rytkonen > --- > .../BensonGlacier/BoardInitPostMem/BoardGpios.h | 20 ++++++------ > .../AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl | 2 ++ > .../PlatformSsdt/Sensors/GenericSpi3.asl | 38 > ++++++++++++++++++++++ > 3 files changed, 50 insertions(+), 10 deletions(-) > create mode 100644 > Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt > /Sensors/GenericSpi3.asl >=20 > diff --git > a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/B > oardGpios.h > b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/B > oardGpios.h > index d72cd80c9..db48c4e85 100644 > --- > a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/B > oardGpios.h > +++ > b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/B > oardGpios.h > @@ -80,13 +80,13 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_N[] =3D > BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA = , NA , > NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, > GPIO_PADBAR+0x0070, NORTH),//Feature: LB > BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA = , NA , > NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, > GPIO_PADBAR+0x0078, NORTH),//Feature: LB > BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA = , NA , > Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,DisPuPd, > GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in Sch: > SIM_CON_CD1, falling edge trigger > - BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_= D, NA , > Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd, > GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N > + BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_= D, NA , > Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd, > GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N > BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA = , NA , > NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, > GPIO_PADBAR+0x0090, NORTH),//Feature: LB > BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA = , NA , > NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, > GPIO_PADBAR+0x0098, NORTH),//Feature: LB > BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA = , NA , > NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, > GPIO_PADBAR+0x00A0, NORTH),//Feature: LB > BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA = , NA , > NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, > GPIO_PADBAR+0x00A8, NORTH),//Feature: LB > BXT_GPIO_PAD_CONF(L"GPIO_22", M0 , GPIO ,GPIO_D= , NA , > NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, > GPIO_PADBAR+0x00B0, NORTH),//Feature: LB > - BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D= , LO , > NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu, > GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N > + BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D= , LO , > NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu, > GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N > BXT_GPIO_PAD_CONF(L"GPIO_24", M0 , GPO ,GPIO_D= , NA , > NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, > GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0 > BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPO ,GPIO_D= , NA , > Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , NA, > GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in Sch: > SATA_ODD_DA_IN > BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPIO ,GPIO_D= , NA , > NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, > GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN > @@ -216,16 +216,16 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_NW > [] =3D > BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M0 , GPI , > GPIO_D , NA , NA , Wake_Disabled, P_20K_H, NA , NA,Hi= zRx0I , > EnPd, GPIO_PADBAR+0x01F8, NORTHWEST), > BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, > GPIO_PADBAR+0x0200, NORTHWEST), > BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, > GPIO_PADBAR+0x0208, NORTHWEST), > - BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , > GPI ,GPIO_D, NA , NA ,Wake_Disabled, P_20K_L, NA , = NA ,NA , > NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP > - BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0218, NORTHWEST), > - BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0220, NORTHWEST), > + BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , > GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , > NA ,NA , NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on > RVP > + BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M0 , > GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , = NA,NA , > NA, GPIO_PADBAR+0x0218, NORTHWEST), > + BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M0 , > GPO ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , > NA,NA , NA, GPIO_PADBAR+0x0220, NORTHWEST), > BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr > BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M0 , GPIO , > GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA= ,NA , > NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr > - BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M0 , GPIO , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0238, NORTHWEST), > - BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M0 , GPIO , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0240, NORTHWEST), > - BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M0 , GPIO , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0248, NORTHWEST), > - BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M0 , GPIO , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0250, NORTHWEST), > - BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M0 , GPIO , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0258, NORTHWEST), > + BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0238, NORTHWEST), > + BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0240, NORTHWEST), > + BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0248, NORTHWEST), > + BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0250, NORTHWEST), > + BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0258, NORTHWEST), > BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0260, NORTHWEST), > BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA > BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA = , > NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, > GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL > diff --git > a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs > dt/PlatformSsdt.asl > b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs > dt/PlatformSsdt.asl > index 1f9da7678..bbab6b63a 100644 > --- > a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs > dt/PlatformSsdt.asl > +++ > b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs > dt/PlatformSsdt.asl > @@ -30,6 +30,7 @@ DefinitionBlock ( > External(\_SB.PCI0.URT2, DeviceObj) > External(\_SB.PCI0.SDIO, DeviceObj) > External(\_SB.PCI0.SPI1, DeviceObj) > + External(\_SB.PCI0.SPI3, DeviceObj) > External(\_SB.GPO0.CWLE, IntObj) > External(\_SB.GPO0.AVBL, IntObj) > External(\_SB.PCI0.SDIO.PSTS, IntObj) > @@ -66,5 +67,6 @@ DefinitionBlock ( >=20 > include ("Fingerprint/Fingerprint_FPC.asl") > include ("SueCreek/SueCreek.asl") > + include ("Sensors/GenericSpi3.asl") > } >=20 > diff --git > a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs > dt/Sensors/GenericSpi3.asl > b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs > dt/Sensors/GenericSpi3.asl > new file mode 100644 > index 000000000..830765bf3 > --- /dev/null > +++ > b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs > dt/Sensors/GenericSpi3.asl > @@ -0,0 +1,38 @@ > +/** @file > + > +Copyright (c) 2017 Intel Corporation. > + > +This program and the accompanying materials > +are licensed and made available under the terms and conditions of the BS= D > License > +which accompanies this distribution. The full text of the license may b= e > found at > +http://opensource.org/licenses/bsd-license.php > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > EXPRESS OR IMPLIED. > + > +**/ > + > +Scope (\_SB.PCI0.SPI3) { > + Device (TP0) { > + Name (_HID, "SPT0001") > + Name (_DDN, "Sensor - SPI3, CS0") > + Name (_CRS, ResourceTemplate () { > + SpiSerialBus ( > + 0, // Chip select (0, 1, 2) > + PolarityLow, // Chip select is active low > + FourWireMode, // Full duplex > + 8, // Bits per word is 8 (byte) > + ControllerInitiated, // Don't care > + 1000000, // 1 MHz > + ClockPolarityLow, // SPI mode 0 > + ClockPhaseFirst, // SPI mode 0 > + "\\_SB.PCI0.SPI3", // SPI host controller > + 0 // Must be 0 > + ) > + }) > + Method (_STA, 0x0, NotSerialized) { > + Return (0xF) > + } > + } > +} > + > -- > 2.14.1.windows.1