From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=david.wei@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5E70321130037 for ; Wed, 13 Jun 2018 20:10:14 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2018 20:10:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,221,1526367600"; d="scan'208";a="47627274" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga008.fm.intel.com with ESMTP; 13 Jun 2018 20:10:13 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Jun 2018 20:10:13 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.82]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.116]) with mapi id 14.03.0319.002; Thu, 14 Jun 2018 11:10:12 +0800 From: "Wei, David" To: "Guo, Mang" , "edk2-devel@lists.01.org" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Set R_SPI_LVSCC Thread-Index: AdQC9arnUvq/1KXCSyOtaAJ85PdkRwAl38sA Date: Thu, 14 Jun 2018 03:10:12 +0000 Message-ID: <89954A0B46707A448411A627AD4EEE34690C3B68@SHSMSX101.ccr.corp.intel.com> References: <22D2C85ED001C54AA20BFE3B0E4751D15269153D@SHSMSX103.ccr.corp.intel.com> In-Reply-To: <22D2C85ED001C54AA20BFE3B0E4751D15269153D@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYjA4MDFlZGYtNGJiYy00M2ZjLWFjOTktZWI2NmI0ZWQwZGM5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiQjZYNzFUUmVFUXBZcEJhTHVkZUlPSTI2bGs1SU9Xcmt4bHdPZit2cHU0XC9VcGNVQ080QjVuTGVEQjhuZEw4VGoifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Set R_SPI_LVSCC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jun 2018 03:10:14 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: zwei4 Thanks, David Wei Intel SSG/STO/UEFI BIOS =20 -----Original Message----- From: Guo, Mang=20 Sent: Wednesday, June 13, 2018 5:05 PM To: edk2-devel@lists.01.org Cc: Wei, David Subject: [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Set R_SPI_LVS= CC Set bit30(VCL) of R_SPI_LVSCC because Vendor Specific Component Capabilitie= s should be locked. Cc: David Wei Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang --- .../BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c | 4 = +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpi= CommonLib/SpiCommon.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Librar= y/BaseScSpiCommonLib/SpiCommon.c index 722f297..4240fd5 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonL= ib/SpiCommon.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonL= ib/SpiCommon.c @@ -1,7 +1,7 @@ /** @file SC SPI Common Driver implements the SPI Host Controller Compatibility In= terface. =20 - Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -74,6 +74,8 @@ SpiProtocolConstructor ( SpiInstance->RegionPermission =3D MmioRead16 (ScSpiBar0 + R_SPI_FRAP); DEBUG ((DEBUG_INFO, "Flash RegionPermission : %0x\n", SpiInstance->Regio= nPermission)); =20 + MmioOr32 (ScSpiBar0 + R_SPI_LVSCC, B_SPI_LVSCC_VCL); + SpiInstance->SfdpVscc0Value =3D MmioRead32 (ScSpiBar0 + R_SPI_LVSCC); DEBUG ((DEBUG_INFO, "Component 0 SFDP VSCC value : %0x\n", SpiInstance->= SfdpVscc0Value)); SpiInstance->SfdpVscc1Value =3D MmioRead32 (ScSpiBar0 + R_SPI_UVSCC); --=20 2.10.1.windows.1