From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=david.wei@intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 97B5921154712 for ; Wed, 26 Sep 2018 20:06:49 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2018 20:06:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,308,1534834800"; d="scan'208";a="89721091" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga002.fm.intel.com with ESMTP; 26 Sep 2018 20:03:51 -0700 Received: from fmsmsx125.amr.corp.intel.com (10.18.125.40) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 26 Sep 2018 20:03:51 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX125.amr.corp.intel.com (10.18.125.40) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 26 Sep 2018 20:03:51 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.220]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.37]) with mapi id 14.03.0319.002; Thu, 27 Sep 2018 11:03:48 +0800 From: "Wei, David" To: "Guo, Mang" , "edk2-devel@lists.01.org" Thread-Topic: [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Set PcdPciePort3Enable Thread-Index: AdRVc+QWW+PiDalnTEmI9l5sRwPKrwAmr8iw Date: Thu, 27 Sep 2018 03:03:48 +0000 Message-ID: <89954A0B46707A448411A627AD4EEE346911E3FF@SHSMSX101.ccr.corp.intel.com> References: <22D2C85ED001C54AA20BFE3B0E4751D1526FBD0C@SHSMSX103.ccr.corp.intel.com> In-Reply-To: <22D2C85ED001C54AA20BFE3B0E4751D1526FBD0C@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYjI1M2NlNGItYmNiYy00NDc5LWFmMzYtOWNkYmFmOTBmZTc1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieWFwcWlaRG1XYU12eXZ0anJSV3dRRlpvV09vTnRrYjhZWmx1ZnB4WU9LZ0NFdHVMc3hTMFJEdmg2MURKUmMzRiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Set PcdPciePort3Enable X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Sep 2018 03:06:49 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: David Wei Thanks, David Wei Intel SSG/STO/UEFI BIOS =20 -----Original Message----- From: Guo, Mang=20 Sent: Wednesday, September 26, 2018 4:36 PM To: edk2-devel@lists.01.org Cc: Wei, David Subject: [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Set PcdPcieP= ort3Enable Use system setup variable to set PcdPciePort3Enable. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang --- .../Board/AuroraGlacier/BoardInitPostMem/BoardInit.c | 5 +++= ++ .../Board/AuroraGlacier/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Board/BensonGlacier/BoardInitPostMem/BoardInit.c | 5 +++= ++ .../Board/BensonGlacier/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit.c | 7 +++= +++- .../Board/LeafHill/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Board/MinnowBoard3/BoardInitPostMem/BoardInit.c | 6 +++= +++ .../Board/MinnowBoard3/BoardInitPostMem/BoardInitPostMem.inf | 1 + .../Board/MinnowBoard3Module/BoardInitPostMem/BoardInit.c | 5 +++= ++ .../Board/MinnowBoard3Module/BoardInitPostMem/BoardInitPostMem.inf | 1 + 10 files changed, 32 insertions(+), 1 deletion(-) diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitP= ostMem/BoardInit.c index ce98086..c61ac86 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInit.c +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInit.c @@ -146,6 +146,11 @@ AuroraGlacierPostMemInitCallback ( PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 1); // I2S2 =20 // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + + // // Add init steps here // // diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/B= oardInitPostMem/BoardInitPostMem.inf index c619332..32aa1da 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInitPostMem.inf @@ -74,6 +74,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitP= ostMem/BoardInit.c index 856d773..c1c4dcd 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInit.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInit.c @@ -146,6 +146,11 @@ BensonGlacierPostMemInitCallback ( PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 1); // I2S2 =20 // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + + // // Add init steps here // // diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/B= oardInitPostMem/BoardInitPostMem.inf index 01d7f27..7dbfed9 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitPostMem.inf @@ -74,6 +74,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Bo= ardInit.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Boa= rdInit.c index 729b15f..5f509a3 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= .c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= .c @@ -151,7 +151,12 @@ LeafHillPostMemInitCallback ( PcdSet8(HdaEndpointI2sRenderSKPVirtualBusId, 5); //I2S6 PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 5); //I2S6 PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 5); //I2S6 - =20 + + // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + // // Add init steps here // diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/Bo= ardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPo= stMem/BoardInitPostMem.inf index 46a6f4b..904b491 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= PostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPostMem/BoardInit= PostMem.inf @@ -74,6 +74,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPos= tMem/BoardInit.c index 3323ee8..d2ed286 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Init.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Init.c @@ -157,6 +157,12 @@ MinnowBoard3PostMemInitCallback ( PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 0); // I2S1 PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 0); // I2S1 =20 + + // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + // // Add init steps here // diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/Boa= rdInitPostMem/BoardInitPostMem.inf index 15d7f46..275a7f4 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= InitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= InitPostMem.inf @@ -70,6 +70,7 @@ gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInit= PostMem/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/= BoardInitPostMem/BoardInit.c index 445897a..6d5817a 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem= /BoardInit.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem= /BoardInit.c @@ -127,6 +127,11 @@ MinnowBoard3ModulePostMemInitCallback ( PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) (SystemConfiguration.ScceMMCHostMa= xSpeed)); =20 // + // Set PcdPciePort3Enable + // + PcdSetBool(PcdPciePort3Enable, SystemConfiguration.PcieRootPortEn[3]); + + // // Add init steps here // // diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInit= PostMem/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/MinnowBoar= d3Module/BoardInitPostMem/BoardInitPostMem.inf index 67708d2..d5b0604 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem= /BoardInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem= /BoardInitPostMem.inf @@ -66,6 +66,7 @@ gPlatformModuleTokenSpaceGuid.PcdOemLogoFileGuid gPlatformModuleTokenSpaceGuid.PcdTianoCoreLogoFileGuid gPlatformModuleTokenSpaceGuid.PcdeMMCHostMaxSpeed + gPlatformModuleTokenSpaceGuid.PcdPciePort3Enable =20 [Guids] gEfiPlatformInfoGuid --=20 2.10.1.windows.1