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* [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fix Type-C video
@ 2018-10-03 16:42 Steele, Kelly
  2018-10-08  1:25 ` Wei, David
  0 siblings, 1 reply; 2+ messages in thread
From: Steele, Kelly @ 2018-10-03 16:42 UTC (permalink / raw)
  To: edk2-devel@lists.01.org; +Cc: Wei, David, Guo, Mang

>From a5d80c8322c30e09a92c0b88cdcec66ee612546f Mon Sep 17 00:00:00 2001
From: Kelly Steele <kelly.steele@intel.com>
Date: Wed, 3 Oct 2018 09:38:36 -0700
Subject: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fix Type-C
video

Enabled Type-C video thru the VBT. Corrected the Type-C debug code
and removed the call to the Type-C debug code.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Kelly Steele <kelly.steele@intel.com>
---
.../BoardInitPostMem/BoardInitMiscs.c              |   5 -
.../MinnowBoard3Module/BoardInitPostMem/TypeC.c    |  77 ++++++------
.../MinnowBoard3Module/BoardInitPostMem/TypeC.h    | 133 ++++++++++++++-------
.../Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin    | Bin 5632 -> 5632 bytes
4 files changed, 130 insertions(+), 85 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
index 99e643f792..4e708e8793 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
@@ -128,11 +128,6 @@ Minnow3ModuleMultiPlatformInfoInit (
   Status = Minnow3ModuleInitializeBoardOemId (PeiServices, PlatformInfoHob);
   Status = Minnow3ModuleInitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
-  //
-  // TypeC MUX AUX mode
-  //
-  MB3SetupTypecMuxAux ();
-
   return EFI_SUCCESS;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
index 7b8d56ab48..12153ab6b0 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
@@ -16,18 +16,20 @@
#include "TypeC.h"
 static MUX_PROGRAMMING_TABLE mMB3MuxTable[] = {
-  // Address   Register                Data             String
-  //====================================================================================
-   {A_GENERAL, R_FIRMWARE_VERSION,     MUX_TABLE_NULL, "Firmware Version Number"},
-   {A_STATUS,  R_CC_STATUS_1,          MUX_TABLE_NULL, "CC_Status_1"},
-   {A_STATUS,  R_CC_STATUS_2,          MUX_TABLE_NULL, "CC_Status_2"},
-   {A_STATUS,  R_CC_STATUS_3,          MUX_TABLE_NULL, "CC_Status_3"},
-   {A_STATUS,  R_MUX_HPD_ASSERT,       MUX_TABLE_NULL, "MUX_In_HPD_Assertion"},
-   {A_STATUS,  R_MUX_STATUS,           MUX_TABLE_NULL, "MUX Status"},
-   {A_STATUS,  R_MUX_DP_TRAINING,      MUX_TABLE_NULL, "MUX_DP_Training_Disable"},
-   {A_STATUS,  R_MUX_DP_AUX_INTERCEPT, MUX_TABLE_NULL, "MUX_DP_AUX_Interception_Disable"},
-   {A_STATUS,  R_MUX_DP_EQ_CONFIG,     MUX_TABLE_NULL, "MUX_DP_EQ_Configuration"},
-   {A_STATUS,  R_MUX_DP_OUTPUT_CONFIG, MUX_TABLE_NULL, "MUX_DP_Output_Configuration"}
+  // Address   Register                Data            OrgData  String
+  //==============================================================================================
+   {A_STATUS,  R_FIRMWARE_VERSION,     MUX_TABLE_NULL, 0x00,    "Firmware Version Number"},         // 0x00
+   {A_STATUS,  R_CC_STATUS,            MUX_TABLE_NULL, 0x00,    "CC_Status"},                       // 0x01
+   {A_MUX,     R_CC_STATUS_1,          MUX_TABLE_NULL, 0x00,    "CC_Status 1"},                     // 0x02
+   {A_MUX,     R_CC_STATUS_2,          MUX_TABLE_NULL, 0x00,    "CC_Status 2"},                     // 0x03
+   {A_MUX,     R_CC_STATUS_3,          MUX_TABLE_NULL, 0x00,    "CC_Status 3"},                     // 0x04
+   {A_MUX,     R_MUX_STATUS,           MUX_TABLE_NULL, 0x00,    "MUX_Status"},                      // 0x05
+   {A_MUX,     R_MUX_USB_STATUS,       MUX_TABLE_NULL, 0x00,    "MUX USB Status"},                  // 0x06
+   {A_MUX,     R_MUX_HPD_ASSERT,       MUX_TABLE_NULL, 0x00,    "MUX_In_HPD_Assertion"},            // 0x07
+   {A_MUX,     R_MUX_DP_TRAINING,      MUX_TABLE_NULL, 0x00,    "MUX_DP_Training_Disable"},         // 0x08
+   {A_MUX,     R_MUX_DP_AUX_INTERCEPT, MUX_TABLE_NULL, 0x00,    "MUX_DP_AUX_Interception_Disable"}, // 0x09
+   {A_MUX,     R_MUX_DP_EQ_CONFIG,     MUX_TABLE_NULL, 0x00,    "MUX_DP_EQ_Configuration"},         // 0x0A
+   {A_MUX,     R_MUX_DP_OUTPUT_CONFIG, MUX_TABLE_NULL, 0x00,    "MUX_DP_Output_Configuration"}      // 0x0B
};
 VOID
@@ -162,6 +164,7 @@ MB3ReadMux (
   RetryCount = MUX_RETRY_COUNT;
   do {
+    MicroSecondDelay (MUX_I2C_DELAY);
     *Data = 0x00;
     Status = ByteReadI2C (PARADE_MUX_I2C_BUS, SlaveAddress, Offset, 1, Data);
   } while ((RetryCount-- > 0) && (EFI_ERROR (Status)));
@@ -182,6 +185,7 @@ MB3WriteMux (
   RetryCount = MUX_RETRY_COUNT;
   do {
+    MicroSecondDelay (MUX_I2C_DELAY);
     Status = ByteWriteI2C (PARADE_MUX_I2C_BUS, SlaveAddress, Offset, 1, Data);
   } while ((RetryCount-- > 0) && (EFI_ERROR (Status)));
@@ -204,15 +208,19 @@ MB3DumpMux (
   // Loop thru device and dump it all
   //
   DEBUG ((DEBUG_INFO, "\n%a(#%4d) - Dump the PS8750 I2C data\n", __FUNCTION__, __LINE__));
-  for (SlaveAddress = 0x08; SlaveAddress <= 0x0E; SlaveAddress++) {
+  for (SlaveAddress = A_STATUS; SlaveAddress <= A_MAX_ADDRESS; SlaveAddress++) {
     for (Offset = 0x00; Offset <= 0xFF; Offset++) {
       Status = MB3ReadMux (SlaveAddress, (UINT8) Offset, &Data[Offset]);
       if (EFI_ERROR (Status)) Data[Offset] = 0xFF;
     }
     DEBUG ((DEBUG_INFO, "\nSlaveAddress = 0x%02x\n", (SlaveAddress << 1)));
-   MB3DumpParagraph (DEBUG_INFO, Data, 256);
+    MB3DumpParagraph (DEBUG_INFO, Data, 256);
   }
   DEBUG ((DEBUG_INFO, "\n"));
+
+  //
+  // Display current HPD status
+  //
   padConfg0.padCnf0 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF0_OFFSET);
   padConfg1.padCnf1 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF1_OFFSET);
   DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d  RxInv = %d\n\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
@@ -225,23 +233,32 @@ MB3SetupTypecMuxAux (
   )
{
   UINT8            Data8;
+  BOOLEAN          I2cQuietFlag;
   UINTN            index;
-  MUX_DATA_TABLE   MuxData;
   BXT_CONF_PAD0    padConfg0;
   BXT_CONF_PAD1    padConfg1;
-  UINT8            *Ptr;
   EFI_STATUS       Status;
   DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...[0x%02x]\n", __FUNCTION__, __LINE__, PARADE_MUX_ADDRESS));
   //
+  // Save off current I2C quiet flag, then enable quiet
+  //
+  I2cQuietFlag = gI2cQuietFlag;
+  gI2cQuietFlag = TRUE;
+
+//KES:    //
+//KES:    // Dump MUX I2C registers
+//KES:    //
+//KES:    MB3DumpMux ();
+
+  //
   // Read/write MUX info
   //
-  Ptr = (UINT8 *) &MuxData;
   for (index = 0; index < (sizeof (mMB3MuxTable) / sizeof (mMB3MuxTable[0])); index++) {
     Status = MB3ReadMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
     DEBUG ((DEBUG_INFO, "%a(#%4d) - %.*a [0x%02x:0x%02x] = 0x%02x (%r)\n", __FUNCTION__, __LINE__, MUX_TABLE_STRING_LENGTH, mMB3MuxTable[index].String, (mMB3MuxTable[index].Address << 1), mMB3MuxTable[index].Register, Data8, Status));
-    Ptr[index] = Data8;
+    mMB3MuxTable[index].OrgData = Data8;
     if ((mMB3MuxTable[index].Data != MUX_TABLE_NULL) && (!EFI_ERROR (Status))) {
       Data8 = (UINT8) (mMB3MuxTable[index].Data & 0x00FF);
       Status = MB3WriteMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
@@ -250,7 +267,7 @@ MB3SetupTypecMuxAux (
       } else {
         Status = MB3ReadMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
         DEBUG ((DEBUG_INFO, "%a(#%4d) - %.*a [0x%02x:0x%02x] = 0x%02x (%r)\n", __FUNCTION__, __LINE__, MUX_TABLE_STRING_LENGTH, mMB3MuxTable[index].String, (mMB3MuxTable[index].Address << 1), mMB3MuxTable[index].Register, Data8, Status));
-        Ptr[index] = Data8;
+        mMB3MuxTable[index].OrgData = Data8;
       }
     }
   }
@@ -263,27 +280,9 @@ MB3SetupTypecMuxAux (
   DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d  RxInv = %d\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
   //
-  // See if we need to assert the HPD on the MUX
+  // Restore I2C quiet flag
   //
-  if ((MuxData.MuxStatus & BIT7) == BIT7) {
-    //
-    // We are in DP mode
-    //
-    if ((MuxData.HpdAssert & BIT7) != BIT7) {
-      //
-      // We need to assert the MUX HPD
-      //
-      Data8  = MuxData.HpdAssert | BIT7;
-      Status = MB3WriteMux (A_STATUS,  R_MUX_HPD_ASSERT, &Data8);
-
-      //
-      // Display HPD
-      //
-      padConfg0.padCnf0 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF0_OFFSET);
-      padConfg1.padCnf1 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF1_OFFSET);
-      DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d  RxInv = %d\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
-    }
-  }
+  gI2cQuietFlag = I2cQuietFlag;
   return EFI_SUCCESS;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
index 0664158159..07fe3d2836 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
@@ -24,60 +24,111 @@
#include <Library/DebugLib.h>
#include <Library/GpioLib.h>
#include <Library/I2cLib.h>
+#include <Library/TimerLib.h>
 //
// Parade Tech PS8750 TypeC MUX
//
-#define PARADE_MUX_I2C_BUS      0x07
-#define PARADE_MUX_ADDRESS      0x50 // 0x10, 0x30, 0x50, 0x90
-#define A_GENERAL               (PARADE_MUX_ADDRESS >> 1)
-#define   R_FIRMWARE_VERSION      0x90
-#define A_STATUS                (A_GENERAL + 0x01)
-#define   R_DP_AUX_SNOOP_BW       0x10
-#define   R_DP_AUX_SNOOP_LC       0x11
-#define   R_DP_AUX_SNOOP_L0       0x12
-#define   R_DP_AUX_SNOOP_L1       0x13
-#define   R_DP_AUX_SNOOP_L2       0x14
-#define   R_DP_AUX_SNOOP_L3       0x15
-#define   R_DP_AUX_SNOOP_D3       0x1E
-#define   R_MUX_STATUS            0x80
-#define   R_MUX_DP_TRAINING       0x83
-#define   R_MUX_DP_AUX_INTERCEPT  0x85
-#define   R_MUX_DP_EQ_CONFIG      0x86
-#define   R_MUX_DP_OUTPUT_CONFIG  0x87
-#define   R_MUX_HPD_ASSERT        0xBC
-#define   R_CC_STATUS_1           0xEC
-#define   R_CC_STATUS_2           0xED
-#define   R_CC_STATUS_3           0xEE
-#define MUX_TABLE_NULL            0xFFFF
-#define MUX_RETRY_COUNT           0x03
-#define MUX_TABLE_STRING_LENGTH   32
+#define PARADE_MUX_I2C_BUS          I2C_SMBUS_BUS
+#define PARADE_MUX_ADDRESS          0x90     // 0x10 0x30 0x50 0x90
+#define A_STATUS                    (PARADE_MUX_ADDRESS >> 1)
+#define   R_CC_STATUS                  0x18
+#define   R_FIRMWARE_VERSION           0x90
+#define A_MUX                       (A_STATUS + 0x01)
+#define   R_DP_AUX_SNOOP_BW            0x10
+#define   R_DP_AUX_SNOOP_LC            0x11
+#define   R_DP_AUX_SNOOP_L0            0x12
+#define   R_DP_AUX_SNOOP_L1            0x13
+#define   R_DP_AUX_SNOOP_L2            0x14
+#define   R_DP_AUX_SNOOP_L3            0x15
+#define   R_SNOOP_D3_STATE             0x1E
+#define   R_MUX_STATUS                 0x80
+#define     B_DP_SELECTED                BIT7
+#define     B_USB_SELECTED               BIT6
+#define     B_FLIPPED                    BIT5
+#define     B_OPERATION_MODE             BIT4
+#define   R_MUX_DP_TRAINING            0x83
+#define     B_LINK_TRAINING_DISABLE      BIT4
+#define   R_MUX_DP_AUX_INTERCEPT       0x85
+#define   R_MUX_DP_EQ_CONFIG           0x86
+#define   R_MUX_DP_OUTPUT_CONFIG       0x87
+#define   R_MUX_USB_SS2C_EQ            0x90
+#define   R_MUX_USB_SS2C_CH_CONFIG     0x91
+#define   R_MUX_USB_SS2C_HS_THRESH     0x93
+#define   R_MUX_USB_SS2C_LFPS_THRESH   0x94
+#define   R_MUX_USB_SS2C_DE            0x95
+#define   R_MUX_USB_SS2C_SWING_ADJ     0x96
+#define   R_MUX_USB_C2SS_CH_CONFIG     0x99
+#define   R_MUX_USB_C2SS_EQ            0x9B
+#define   R_MUX_USB_C2SS_HS_THRESH     0x9C
+#define   R_MUX_USB_C2SS_LFPS_THRESH   0x9D
+#define   R_MUX_USB_C2SS_DE            0x9E
+#define   R_MUX_USB_C2SS_SWING_ADJ     0x9F
+#define   R_MUX_USB_DCI_CFG            0xA3
+#define   R_MUX_HPD_ASSERT             0xBC
+#define     B_IN_HPD                     BIT7
+#define     B_HPD_IRQ                    BIT1
+#define   R_CC_STATUS_1                0xEC
+#define   R_CC_STATUS_2                0xED
+#define   R_CC_STATUS_3                0xEE
+#define   R_MUX_USB_STATUS             0xF5
+#define A_PDO                       (A_STATUS + 0x05)
+#define   R_INITIATED_PDO_0            0x00
+#define   R_INITIATED_PDO_1            0x01
+#define   R_INITIATED_PDO_2            0x02
+#define   R_INITIATED_PDO_3            0x03
+#define   R_INITIATED_PDO_4            0x04
+#define   R_INITIATED_PDO_5            0x05
+#define   R_INITIATED_PDO_6            0x06
+#define   R_INITIATED_PDO_7            0x07
+#define   R_INITIATED_PDO_8            0x08
+#define   R_INITIATED_PDO_9            0x09
+#define   R_INITIATED_PDO_A            0x0A
+#define   R_INITIATED_PDO_B            0x0B
+#define   R_INITIATED_PDO_C            0x0C
+#define   R_INITIATED_PDO_D            0x0D
+#define   R_INITIATED_PDO_E            0x0E
+#define   R_INITIATED_PDO_F            0x0F
+#define   R_CHARGER_INITIATED_PDOs_0   0x10
+#define   R_CHARGER_INITIATED_PDOs_1   0x11
+#define   R_CHARGER_INITIATED_PDOs_2   0x12
+#define   R_CHARGER_INITIATED_PDOs_3   0x13
+#define   R_CHARGER_INITIATED_PDOs_4   0x14
+#define   R_CHARGER_INITIATED_PDOs_5   0x15
+#define   R_CHARGER_INITIATED_PDOs_6   0x16
+#define   R_CHARGER_INITIATED_PDOs_7   0x17
+#define   R_CHARGER_INITIATED_PDOs_8   0x18
+#define   R_CHARGER_INITIATED_PDOs_9   0x19
+#define   R_CHARGER_INITIATED_PDOs_A   0x1A
+#define   R_CHARGER_INITIATED_PDOs_B   0x1B
+#define   R_CHARGER_INITIATED_PDOs_C   0x1C
+#define   R_CHARGER_INITIATED_PDOs_D   0x1D
+#define   R_CHARGER_INITIATED_PDOs_E   0x1E
+#define   R_CHARGER_INITIATED_PDOs_F   0x1F
+#define   R_SINK_CHOSEN_PDO_INDEX      0x20
+#define   R_SINK_REQUEST_CURRENT       0x21
+#define   R_PS_RDY_TRIGGER             0x22
+#define   R_DP_ALT_MODE_STATUS         0x2F
+#define   R_CHARGER_PDO_SELECT_INDEX   0x30
+#define   R_CHARGER_CURRENT_REQUEST    0x31
+#define   R_REQUEST_MESSAGE_TRIGGER    0x32
+#define   R_CHARGER_PS_RDY_STATUS      0x33
+#define A_MAX_ADDRESS               (A_STATUS + 0x06)
+#define MUX_TABLE_NULL              0xFFFF
+#define MUX_RETRY_COUNT             0x03
+#define MUX_TABLE_STRING_LENGTH     32
-#define MUX_HPD_GPIO              NW_GPIO_200
+#define MUX_HPD_GPIO                NW_GPIO_200
+#define MUX_I2C_DELAY               500
 typedef struct {
   UINT8         Address;
   UINT8         Register;
   UINT16        Data;
+  UINT8         OrgData;
   CHAR8         String[MUX_TABLE_STRING_LENGTH];
} MUX_PROGRAMMING_TABLE;
-typedef struct {
-  //
-  // These UINT8 elements need to match the MUX_PROGRAMMING_TABLE list so we can use the Index to reference them
-  //
-  UINT8         FirmwareVersion;  // Offset 0
-  UINT8         CcStatus1;        // Offset 1
-  UINT8         CcStatus2;        // Offset 2
-  UINT8         CcStatus3;        // Offset 3
-  UINT8         MuxStatus;        // Offset 4
-  UINT8         HpdAssert;        // Offset 5
-  UINT8         DpTraining;       // Offset 6
-  UINT8         DpAuxIntercept;   // Offset 7
-  UINT8         DpEqConfig;       // Offset 8
-  UINT8         DpOutputConfig;   // Offset 9
-} MUX_DATA_TABLE;
-
EFI_STATUS
EFIAPI
MB3SetupTypecMuxAux (
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin
index 8a432de2d9717d1916e552bd20e7dfc627861bca..48565f431e281bb50910479d03ab6caa6aa7980c 100644
GIT binary patch
delta 25
gcmZqBY0#M<#T?9FFgcJ>c%y*;BcsD+N5=gk09KX;d;kCd

delta 25
gcmZqBY0#M<#XOn8U~(X%@J0gxMn;Csj*R<709lp>d;kCd

--
2.11.0.windows.1



^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fix Type-C video
  2018-10-03 16:42 [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fix Type-C video Steele, Kelly
@ 2018-10-08  1:25 ` Wei, David
  0 siblings, 0 replies; 2+ messages in thread
From: Wei, David @ 2018-10-08  1:25 UTC (permalink / raw)
  To: Steele, Kelly, edk2-devel@lists.01.org; +Cc: Guo, Mang, Wei, David

Hi Kelly,

Below comments should be removed. Other changes looks good to me.

Reviewed-by: David Wei <david.wei@intel.com>

+
+//KES:    //
+//KES:    // Dump MUX I2C registers
+//KES:    //
+//KES:    MB3DumpMux ();
+
+  //

Thanks,
David  Wei

Intel SSG/STO/UEFI BIOS

From: Steele, Kelly
Sent: Thursday, October 4, 2018 12:42 AM
To: edk2-devel@lists.01.org
Cc: Wei, David <david.wei@intel.com>; Guo, Mang <mang.guo@intel.com>
Subject: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fix Type-C video

>From a5d80c8322c30e09a92c0b88cdcec66ee612546f Mon Sep 17 00:00:00 2001
From: Kelly Steele <kelly.steele@intel.com<mailto:kelly.steele@intel.com>>
Date: Wed, 3 Oct 2018 09:38:36 -0700
Subject: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fix Type-C
video

Enabled Type-C video thru the VBT. Corrected the Type-C debug code
and removed the call to the Type-C debug code.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Kelly Steele <kelly.steele@intel.com<mailto:kelly.steele@intel.com>>
---
.../BoardInitPostMem/BoardInitMiscs.c              |   5 -
.../MinnowBoard3Module/BoardInitPostMem/TypeC.c    |  77 ++++++------
.../MinnowBoard3Module/BoardInitPostMem/TypeC.h    | 133 ++++++++++++++-------
.../Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin    | Bin 5632 -> 5632 bytes
4 files changed, 130 insertions(+), 85 deletions(-)

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
index 99e643f792..4e708e8793 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/BoardInitMiscs.c
@@ -128,11 +128,6 @@ Minnow3ModuleMultiPlatformInfoInit (
   Status = Minnow3ModuleInitializeBoardOemId (PeiServices, PlatformInfoHob);
   Status = Minnow3ModuleInitializeBoardSsidSvid (PeiServices, PlatformInfoHob);

-  //
-  // TypeC MUX AUX mode
-  //
-  MB3SetupTypecMuxAux ();
-
   return EFI_SUCCESS;
}

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
index 7b8d56ab48..12153ab6b0 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.c
@@ -16,18 +16,20 @@
#include "TypeC.h"

 static MUX_PROGRAMMING_TABLE mMB3MuxTable[] = {
-  // Address   Register                Data             String
-  //====================================================================================
-   {A_GENERAL, R_FIRMWARE_VERSION,     MUX_TABLE_NULL, "Firmware Version Number"},
-   {A_STATUS,  R_CC_STATUS_1,          MUX_TABLE_NULL, "CC_Status_1"},
-   {A_STATUS,  R_CC_STATUS_2,          MUX_TABLE_NULL, "CC_Status_2"},
-   {A_STATUS,  R_CC_STATUS_3,          MUX_TABLE_NULL, "CC_Status_3"},
-   {A_STATUS,  R_MUX_HPD_ASSERT,       MUX_TABLE_NULL, "MUX_In_HPD_Assertion"},
-   {A_STATUS,  R_MUX_STATUS,           MUX_TABLE_NULL, "MUX Status"},
-   {A_STATUS,  R_MUX_DP_TRAINING,      MUX_TABLE_NULL, "MUX_DP_Training_Disable"},
-   {A_STATUS,  R_MUX_DP_AUX_INTERCEPT, MUX_TABLE_NULL, "MUX_DP_AUX_Interception_Disable"},
-   {A_STATUS,  R_MUX_DP_EQ_CONFIG,     MUX_TABLE_NULL, "MUX_DP_EQ_Configuration"},
-   {A_STATUS,  R_MUX_DP_OUTPUT_CONFIG, MUX_TABLE_NULL, "MUX_DP_Output_Configuration"}
+  // Address   Register                Data            OrgData  String
+  //==============================================================================================
+   {A_STATUS,  R_FIRMWARE_VERSION,     MUX_TABLE_NULL, 0x00,    "Firmware Version Number"},         // 0x00
+   {A_STATUS,  R_CC_STATUS,            MUX_TABLE_NULL, 0x00,    "CC_Status"},                       // 0x01
+   {A_MUX,     R_CC_STATUS_1,          MUX_TABLE_NULL, 0x00,    "CC_Status 1"},                     // 0x02
+   {A_MUX,     R_CC_STATUS_2,          MUX_TABLE_NULL, 0x00,    "CC_Status 2"},                     // 0x03
+   {A_MUX,     R_CC_STATUS_3,          MUX_TABLE_NULL, 0x00,    "CC_Status 3"},                     // 0x04
+   {A_MUX,     R_MUX_STATUS,           MUX_TABLE_NULL, 0x00,    "MUX_Status"},                      // 0x05
+   {A_MUX,     R_MUX_USB_STATUS,       MUX_TABLE_NULL, 0x00,    "MUX USB Status"},                  // 0x06
+   {A_MUX,     R_MUX_HPD_ASSERT,       MUX_TABLE_NULL, 0x00,    "MUX_In_HPD_Assertion"},            // 0x07
+   {A_MUX,     R_MUX_DP_TRAINING,      MUX_TABLE_NULL, 0x00,    "MUX_DP_Training_Disable"},         // 0x08
+   {A_MUX,     R_MUX_DP_AUX_INTERCEPT, MUX_TABLE_NULL, 0x00,    "MUX_DP_AUX_Interception_Disable"}, // 0x09
+   {A_MUX,     R_MUX_DP_EQ_CONFIG,     MUX_TABLE_NULL, 0x00,    "MUX_DP_EQ_Configuration"},         // 0x0A
+   {A_MUX,     R_MUX_DP_OUTPUT_CONFIG, MUX_TABLE_NULL, 0x00,    "MUX_DP_Output_Configuration"}      // 0x0B
};

 VOID
@@ -162,6 +164,7 @@ MB3ReadMux (

   RetryCount = MUX_RETRY_COUNT;
   do {
+    MicroSecondDelay (MUX_I2C_DELAY);
     *Data = 0x00;
     Status = ByteReadI2C (PARADE_MUX_I2C_BUS, SlaveAddress, Offset, 1, Data);
   } while ((RetryCount-- > 0) && (EFI_ERROR (Status)));
@@ -182,6 +185,7 @@ MB3WriteMux (

   RetryCount = MUX_RETRY_COUNT;
   do {
+    MicroSecondDelay (MUX_I2C_DELAY);
     Status = ByteWriteI2C (PARADE_MUX_I2C_BUS, SlaveAddress, Offset, 1, Data);
   } while ((RetryCount-- > 0) && (EFI_ERROR (Status)));

@@ -204,15 +208,19 @@ MB3DumpMux (
   // Loop thru device and dump it all
   //
   DEBUG ((DEBUG_INFO, "\n%a(#%4d) - Dump the PS8750 I2C data\n", __FUNCTION__, __LINE__));
-  for (SlaveAddress = 0x08; SlaveAddress <= 0x0E; SlaveAddress++) {
+  for (SlaveAddress = A_STATUS; SlaveAddress <= A_MAX_ADDRESS; SlaveAddress++) {
     for (Offset = 0x00; Offset <= 0xFF; Offset++) {
       Status = MB3ReadMux (SlaveAddress, (UINT8) Offset, &Data[Offset]);
       if (EFI_ERROR (Status)) Data[Offset] = 0xFF;
     }
     DEBUG ((DEBUG_INFO, "\nSlaveAddress = 0x%02x\n", (SlaveAddress << 1)));
-   MB3DumpParagraph (DEBUG_INFO, Data, 256);
+    MB3DumpParagraph (DEBUG_INFO, Data, 256);
   }
   DEBUG ((DEBUG_INFO, "\n"));
+
+  //
+  // Display current HPD status
+  //
   padConfg0.padCnf0 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF0_OFFSET);
   padConfg1.padCnf1 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF1_OFFSET);
   DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d  RxInv = %d\n\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
@@ -225,23 +233,32 @@ MB3SetupTypecMuxAux (
   )
{
   UINT8            Data8;
+  BOOLEAN          I2cQuietFlag;
   UINTN            index;
-  MUX_DATA_TABLE   MuxData;
   BXT_CONF_PAD0    padConfg0;
   BXT_CONF_PAD1    padConfg1;
-  UINT8            *Ptr;
   EFI_STATUS       Status;

   DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...[0x%02x]\n", __FUNCTION__, __LINE__, PARADE_MUX_ADDRESS));

   //
+  // Save off current I2C quiet flag, then enable quiet
+  //
+  I2cQuietFlag = gI2cQuietFlag;
+  gI2cQuietFlag = TRUE;
+
+//KES:    //
+//KES:    // Dump MUX I2C registers
+//KES:    //
+//KES:    MB3DumpMux ();
+
+  //
   // Read/write MUX info
   //
-  Ptr = (UINT8 *) &MuxData;
   for (index = 0; index < (sizeof (mMB3MuxTable) / sizeof (mMB3MuxTable[0])); index++) {
     Status = MB3ReadMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
     DEBUG ((DEBUG_INFO, "%a(#%4d) - %.*a [0x%02x:0x%02x] = 0x%02x (%r)\n", __FUNCTION__, __LINE__, MUX_TABLE_STRING_LENGTH, mMB3MuxTable[index].String, (mMB3MuxTable[index].Address << 1), mMB3MuxTable[index].Register, Data8, Status));
-    Ptr[index] = Data8;
+    mMB3MuxTable[index].OrgData = Data8;
     if ((mMB3MuxTable[index].Data != MUX_TABLE_NULL) && (!EFI_ERROR (Status))) {
       Data8 = (UINT8) (mMB3MuxTable[index].Data & 0x00FF);
       Status = MB3WriteMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
@@ -250,7 +267,7 @@ MB3SetupTypecMuxAux (
       } else {
         Status = MB3ReadMux (mMB3MuxTable[index].Address, mMB3MuxTable[index].Register, &Data8);
         DEBUG ((DEBUG_INFO, "%a(#%4d) - %.*a [0x%02x:0x%02x] = 0x%02x (%r)\n", __FUNCTION__, __LINE__, MUX_TABLE_STRING_LENGTH, mMB3MuxTable[index].String, (mMB3MuxTable[index].Address << 1), mMB3MuxTable[index].Register, Data8, Status));
-        Ptr[index] = Data8;
+        mMB3MuxTable[index].OrgData = Data8;
       }
     }
   }
@@ -263,27 +280,9 @@ MB3SetupTypecMuxAux (
   DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d  RxInv = %d\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));

   //
-  // See if we need to assert the HPD on the MUX
+  // Restore I2C quiet flag
   //
-  if ((MuxData.MuxStatus & BIT7) == BIT7) {
-    //
-    // We are in DP mode
-    //
-    if ((MuxData.HpdAssert & BIT7) != BIT7) {
-      //
-      // We need to assert the MUX HPD
-      //
-      Data8  = MuxData.HpdAssert | BIT7;
-      Status = MB3WriteMux (A_STATUS,  R_MUX_HPD_ASSERT, &Data8);
-
-      //
-      // Display HPD
-      //
-      padConfg0.padCnf0 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF0_OFFSET);
-      padConfg1.padCnf1 = GpioPadRead (MUX_HPD_GPIO + BXT_GPIO_PAD_CONF1_OFFSET);
-      DEBUG ((DEBUG_INFO, "%a(#%4d) - MUX_HPD_GPIO Rx = %d  RxInv = %d\n", __FUNCTION__, __LINE__, padConfg0.r.GPIORxState, padConfg0.r.RXINV));
-    }
-  }
+  gI2cQuietFlag = I2cQuietFlag;

   return EFI_SUCCESS;
}
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
index 0664158159..07fe3d2836 100644
--- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/BoardInitPostMem/TypeC.h
@@ -24,60 +24,111 @@
#include <Library/DebugLib.h>
#include <Library/GpioLib.h>
#include <Library/I2cLib.h>
+#include <Library/TimerLib.h>

 //
// Parade Tech PS8750 TypeC MUX
//
-#define PARADE_MUX_I2C_BUS      0x07
-#define PARADE_MUX_ADDRESS      0x50 // 0x10, 0x30, 0x50, 0x90
-#define A_GENERAL               (PARADE_MUX_ADDRESS >> 1)
-#define   R_FIRMWARE_VERSION      0x90
-#define A_STATUS                (A_GENERAL + 0x01)
-#define   R_DP_AUX_SNOOP_BW       0x10
-#define   R_DP_AUX_SNOOP_LC       0x11
-#define   R_DP_AUX_SNOOP_L0       0x12
-#define   R_DP_AUX_SNOOP_L1       0x13
-#define   R_DP_AUX_SNOOP_L2       0x14
-#define   R_DP_AUX_SNOOP_L3       0x15
-#define   R_DP_AUX_SNOOP_D3       0x1E
-#define   R_MUX_STATUS            0x80
-#define   R_MUX_DP_TRAINING       0x83
-#define   R_MUX_DP_AUX_INTERCEPT  0x85
-#define   R_MUX_DP_EQ_CONFIG      0x86
-#define   R_MUX_DP_OUTPUT_CONFIG  0x87
-#define   R_MUX_HPD_ASSERT        0xBC
-#define   R_CC_STATUS_1           0xEC
-#define   R_CC_STATUS_2           0xED
-#define   R_CC_STATUS_3           0xEE
-#define MUX_TABLE_NULL            0xFFFF
-#define MUX_RETRY_COUNT           0x03
-#define MUX_TABLE_STRING_LENGTH   32
+#define PARADE_MUX_I2C_BUS          I2C_SMBUS_BUS
+#define PARADE_MUX_ADDRESS          0x90     // 0x10 0x30 0x50 0x90
+#define A_STATUS                    (PARADE_MUX_ADDRESS >> 1)
+#define   R_CC_STATUS                  0x18
+#define   R_FIRMWARE_VERSION           0x90
+#define A_MUX                       (A_STATUS + 0x01)
+#define   R_DP_AUX_SNOOP_BW            0x10
+#define   R_DP_AUX_SNOOP_LC            0x11
+#define   R_DP_AUX_SNOOP_L0            0x12
+#define   R_DP_AUX_SNOOP_L1            0x13
+#define   R_DP_AUX_SNOOP_L2            0x14
+#define   R_DP_AUX_SNOOP_L3            0x15
+#define   R_SNOOP_D3_STATE             0x1E
+#define   R_MUX_STATUS                 0x80
+#define     B_DP_SELECTED                BIT7
+#define     B_USB_SELECTED               BIT6
+#define     B_FLIPPED                    BIT5
+#define     B_OPERATION_MODE             BIT4
+#define   R_MUX_DP_TRAINING            0x83
+#define     B_LINK_TRAINING_DISABLE      BIT4
+#define   R_MUX_DP_AUX_INTERCEPT       0x85
+#define   R_MUX_DP_EQ_CONFIG           0x86
+#define   R_MUX_DP_OUTPUT_CONFIG       0x87
+#define   R_MUX_USB_SS2C_EQ            0x90
+#define   R_MUX_USB_SS2C_CH_CONFIG     0x91
+#define   R_MUX_USB_SS2C_HS_THRESH     0x93
+#define   R_MUX_USB_SS2C_LFPS_THRESH   0x94
+#define   R_MUX_USB_SS2C_DE            0x95
+#define   R_MUX_USB_SS2C_SWING_ADJ     0x96
+#define   R_MUX_USB_C2SS_CH_CONFIG     0x99
+#define   R_MUX_USB_C2SS_EQ            0x9B
+#define   R_MUX_USB_C2SS_HS_THRESH     0x9C
+#define   R_MUX_USB_C2SS_LFPS_THRESH   0x9D
+#define   R_MUX_USB_C2SS_DE            0x9E
+#define   R_MUX_USB_C2SS_SWING_ADJ     0x9F
+#define   R_MUX_USB_DCI_CFG            0xA3
+#define   R_MUX_HPD_ASSERT             0xBC
+#define     B_IN_HPD                     BIT7
+#define     B_HPD_IRQ                    BIT1
+#define   R_CC_STATUS_1                0xEC
+#define   R_CC_STATUS_2                0xED
+#define   R_CC_STATUS_3                0xEE
+#define   R_MUX_USB_STATUS             0xF5
+#define A_PDO                       (A_STATUS + 0x05)
+#define   R_INITIATED_PDO_0            0x00
+#define   R_INITIATED_PDO_1            0x01
+#define   R_INITIATED_PDO_2            0x02
+#define   R_INITIATED_PDO_3            0x03
+#define   R_INITIATED_PDO_4            0x04
+#define   R_INITIATED_PDO_5            0x05
+#define   R_INITIATED_PDO_6            0x06
+#define   R_INITIATED_PDO_7            0x07
+#define   R_INITIATED_PDO_8            0x08
+#define   R_INITIATED_PDO_9            0x09
+#define   R_INITIATED_PDO_A            0x0A
+#define   R_INITIATED_PDO_B            0x0B
+#define   R_INITIATED_PDO_C            0x0C
+#define   R_INITIATED_PDO_D            0x0D
+#define   R_INITIATED_PDO_E            0x0E
+#define   R_INITIATED_PDO_F            0x0F
+#define   R_CHARGER_INITIATED_PDOs_0   0x10
+#define   R_CHARGER_INITIATED_PDOs_1   0x11
+#define   R_CHARGER_INITIATED_PDOs_2   0x12
+#define   R_CHARGER_INITIATED_PDOs_3   0x13
+#define   R_CHARGER_INITIATED_PDOs_4   0x14
+#define   R_CHARGER_INITIATED_PDOs_5   0x15
+#define   R_CHARGER_INITIATED_PDOs_6   0x16
+#define   R_CHARGER_INITIATED_PDOs_7   0x17
+#define   R_CHARGER_INITIATED_PDOs_8   0x18
+#define   R_CHARGER_INITIATED_PDOs_9   0x19
+#define   R_CHARGER_INITIATED_PDOs_A   0x1A
+#define   R_CHARGER_INITIATED_PDOs_B   0x1B
+#define   R_CHARGER_INITIATED_PDOs_C   0x1C
+#define   R_CHARGER_INITIATED_PDOs_D   0x1D
+#define   R_CHARGER_INITIATED_PDOs_E   0x1E
+#define   R_CHARGER_INITIATED_PDOs_F   0x1F
+#define   R_SINK_CHOSEN_PDO_INDEX      0x20
+#define   R_SINK_REQUEST_CURRENT       0x21
+#define   R_PS_RDY_TRIGGER             0x22
+#define   R_DP_ALT_MODE_STATUS         0x2F
+#define   R_CHARGER_PDO_SELECT_INDEX   0x30
+#define   R_CHARGER_CURRENT_REQUEST    0x31
+#define   R_REQUEST_MESSAGE_TRIGGER    0x32
+#define   R_CHARGER_PS_RDY_STATUS      0x33
+#define A_MAX_ADDRESS               (A_STATUS + 0x06)
+#define MUX_TABLE_NULL              0xFFFF
+#define MUX_RETRY_COUNT             0x03
+#define MUX_TABLE_STRING_LENGTH     32

-#define MUX_HPD_GPIO              NW_GPIO_200
+#define MUX_HPD_GPIO                NW_GPIO_200
+#define MUX_I2C_DELAY               500

 typedef struct {
   UINT8         Address;
   UINT8         Register;
   UINT16        Data;
+  UINT8         OrgData;
   CHAR8         String[MUX_TABLE_STRING_LENGTH];
} MUX_PROGRAMMING_TABLE;

-typedef struct {
-  //
-  // These UINT8 elements need to match the MUX_PROGRAMMING_TABLE list so we can use the Index to reference them
-  //
-  UINT8         FirmwareVersion;  // Offset 0
-  UINT8         CcStatus1;        // Offset 1
-  UINT8         CcStatus2;        // Offset 2
-  UINT8         CcStatus3;        // Offset 3
-  UINT8         MuxStatus;        // Offset 4
-  UINT8         HpdAssert;        // Offset 5
-  UINT8         DpTraining;       // Offset 6
-  UINT8         DpAuxIntercept;   // Offset 7
-  UINT8         DpEqConfig;       // Offset 8
-  UINT8         DpOutputConfig;   // Offset 9
-} MUX_DATA_TABLE;
-
EFI_STATUS
EFIAPI
MB3SetupTypecMuxAux (
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Vbt/VbtBxtMipi.bin
index 8a432de2d9717d1916e552bd20e7dfc627861bca..48565f431e281bb50910479d03ab6caa6aa7980c 100644
GIT binary patch
delta 25
gcmZqBY0#M<#T?9FFgcJ>c%y*;BcsD+N5=gk09KX;d;kCd

delta 25
gcmZqBY0#M<#XOn8U~(X%@J0gxMn;Csj*R<709lp>d;kCd

--
2.11.0.windows.1



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2018-10-03 16:42 [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Fix Type-C video Steele, Kelly
2018-10-08  1:25 ` Wei, David

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