From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.5889.1634117507223269891 for ; Wed, 13 Oct 2021 02:31:47 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pierre.gondois@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5CE861063; Wed, 13 Oct 2021 02:31:46 -0700 (PDT) Received: from [192.168.1.16] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3FCCA3F70D; Wed, 13 Oct 2021 02:31:45 -0700 (PDT) Message-ID: <89b9b4f9-35ff-3503-a9f5-e319fac6effe@arm.com> Date: Wed, 13 Oct 2021 10:31:43 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [edk2-devel] [PATCH v2 2/7] Silicon/ARM/NeoverseN1Soc: Define new PCDs and configure memory map To: devel@edk2.groups.io, khasim.mohammed@arm.com Cc: Chandni Cherukuri , Sami Mujawar References: <20211010182956.13526-1-khasim.mohammed@arm.com> <20211010182956.13526-3-khasim.mohammed@arm.com> From: "PierreGondois" In-Reply-To: <20211010182956.13526-3-khasim.mohammed@arm.com> Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Khasim and Chandni, The patch looks good to me, Reviewed-by: Pierre Gondois Regards, Pierre On 10/10/21 19:29, Khasim Mohammed via groups.io wrote: > This patch introduces new PCDs required to enable > chip to chip interface and corresponding memory map is updated. > > Signed-off-by: Chandni Cherukuri > Signed-off-by: Khasim Syed Mohammed > --- > .../Library/PlatformLib/PlatformLib.inf | 28 +++++-- > .../Library/PlatformLib/PlatformLibMem.c | 84 ++++++++++++++++--- > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 35 +++++++- > 3 files changed, 125 insertions(+), 22 deletions(-) > > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > index 166c9e0444..8e2154aadf 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf > @@ -1,6 +1,7 @@ > ## @file > +# Platform Library for N1Sdp. > # > -# Copyright (c) 2018-2020, ARM Limited. All rights reserved. > +# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -29,13 +30,17 @@ > AArch64/Helper.S | GCC > > [FixedPcd] > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > - > - gArmTokenSpaceGuid.PcdSystemMemoryBase > - gArmTokenSpaceGuid.PcdSystemMemorySize > - gArmTokenSpaceGuid.PcdArmPrimaryCore > - gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > - > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize > + gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base > @@ -45,7 +50,12 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize > > - gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base > + gArmTokenSpaceGuid.PcdArmPrimaryCore > + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > > [Guids] > gEfiHobListGuid ## CONSUMES ## SystemTable > diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > index f9b3d03753..1c4a445c5e 100644 > --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c > @@ -1,9 +1,9 @@ > /** @file > -* > -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > -* > -* SPDX-License-Identifier: BSD-2-Clause-Patent > -* > + > + Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > **/ > > #include > @@ -13,7 +13,7 @@ > #include > > // The total number of descriptors, including the final "end-of-table" descriptor. > -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 13 > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 > > /** > Returns the Virtual Memory Map of the platform. > @@ -21,21 +21,23 @@ > This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU > on your platform. > > - @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing > - a Physical-to-Virtual Memory mapping. This array > - must be ended by a zero-filled entry. > + @param[in] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing > + a Physical-to-Virtual Memory mapping. This array > + must be ended by a zero-filled entry. > **/ > VOID > ArmPlatformGetVirtualMemoryMap ( > IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > ) > { > - UINTN Index = 0; > + UINTN Index; > ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > NEOVERSEN1SOC_PLAT_INFO *PlatInfo; > UINT64 DramBlock2Size; > + UINT64 RemoteDdrSize; > > + Index = 0; > PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; > DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - > NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * > @@ -55,6 +57,24 @@ ArmPlatformGetVirtualMemoryMap ( > FixedPcdGet64 (PcdDramBlock2Base), > DramBlock2Size); > > + if (PlatInfo->MultichipMode == 1) { > + RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdSystemMemoryBase), > + PcdGet64 (PcdSystemMemorySize) > + ); > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + FixedPcdGet64 (PcdExtMemorySpace) + FixedPcdGet64 (PcdDramBlock2Base), > + RemoteDdrSize > + ); > + } > + > ASSERT (VirtualMemoryMap != NULL); > Index = 0; > > @@ -114,6 +134,32 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length = PcdGet64 (PcdPcieMmio64Size); > VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > + // CCIX RC Configuration Space > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixRootPortConfigBaseAddress); > + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixRootPortConfigBaseAddress); > + VirtualMemoryTable[Index].Length = PcdGet32 (PcdCcixRootPortConfigBaseSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // CCIX ECAM Configuration Space > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixExpressBaseAddress); > + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixExpressBaseAddress); > + VirtualMemoryTable[Index].Length = (FixedPcdGet32 (PcdCcixBusMax) - > + FixedPcdGet32 (PcdCcixBusMin) + 1) * > + SIZE_1MB; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // CCIX MMIO32 Memory Space > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdCcixMmio32Base); > + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdCcixMmio32Base); > + VirtualMemoryTable[Index].Length = PcdGet32 (PcdCcixMmio32Size); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > + // CCIX MMIO64 Memory Space > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdCcixMmio64Base); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdCcixMmio64Base); > + VirtualMemoryTable[Index].Length = PcdGet64 (PcdCcixMmio64Size); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > // SubSystem Pheripherals - UART0 > VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_UART0_BASE; > VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_UART0_BASE; > @@ -138,6 +184,24 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ; > VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > + if (PlatInfo->MultichipMode == 1) { > + //Remote DDR (2GB) > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) + > + PcdGet64 (PcdSystemMemoryBase); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdExtMemorySpace) + > + PcdGet64 (PcdSystemMemoryBase); > + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; > + > + //Remote DDR > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) + > + PcdGet64 (PcdDramBlock2Base); > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdExtMemorySpace) + > + PcdGet64 (PcdDramBlock2Base); > + VirtualMemoryTable[Index].Length = RemoteDdrSize; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; > + } > + > // End of Table > VirtualMemoryTable[++Index].PhysicalBase = 0; > VirtualMemoryTable[Index].VirtualBase = 0; > diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > index 54b793a937..eea2d58402 100644 > --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec > @@ -1,5 +1,7 @@ > +## @file > +# Describes the entire platform configuration. > # > -# Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. > +# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -33,8 +35,8 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax|17|UINT32|0x00000005 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin|0|UINT32|0x00000006 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase|0x0|UINT32|0x00000007 > - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x00FFFFFF|UINT32|0x00000008 > - gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x01000000|UINT32|0x00000009 > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase|0x001FFFF|UINT32|0x00000008 > + gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize|0x020000|UINT32|0x00000009 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation|0x75200000|UINT32|0x0000000A > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base|0x71200000|UINT32|0x0000000B > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase|0x751FFFFF|UINT32|0x0000000C > @@ -44,3 +46,30 @@ > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase|0x28FFFFFFFF|UINT64|0x00000010 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size|0x2000000000|UINT64|0x00000011 > gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation|0x0|UINT64|0x00000012 > + > + # CCIX > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount|18|UINT32|0x00000016 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax|17|UINT32|0x00000017 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin|0|UINT32|0x00000018 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress|0x68000000|UINT32|0x00000019 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase|0x0|UINT32|0x0000001A > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase|0x01FFFF|UINT32|0x0000001B > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize|0x020000|UINT32|0x0000001C > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation|0x6D200000|UINT32|0x00000001D > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base|0x69200000|UINT32|0x0000001E > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase|0x6D1FFFFF|UINT32|0x00000001F > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size|0x04000000|UINT32|0x00000020 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation|0x0|UINT32|0x00000021 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base|0x2900000000|UINT64|0x00000022 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase|0x48FFFFFFFF|UINT64|0x00000023 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size|0x2000000000|UINT64|0x00000024 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation|0x0|UINT64|0x00000025 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress|0x62000000|UINT32|0x00000026 > + gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize|0x00001000|UINT32|0x00000027 > + > + gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace|0x40000000000|UINT64|0x00000029 > + > + # Remote Chip PCIe > + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieIoTranslation|0x40075200000|UINT64|0x0000004A > + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004B > + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x0000004C